| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | soc/intel/alderlake: Correct TCSS XHCI Port status offset | Sridhar Siricilla | 2021-06-08 | 1 | -2/+2 |
| * | soc/intel/alderlake: Add soc_get_xhci_usb_info() for elog support | Tim Wawrzynczak | 2021-02-24 | 1 | -0/+44 |
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index : coreboot.git | |
| Coreboot firmware sources | coreboot |
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