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path: root/src/soc/intel/alderlake
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* soc/intel/alderlake: Add GFx Device ID 0x46b3Meera Ravindranath2021-06-211-0/+1
* soc/intel/alderlake: Add TBT PCIe root ports enablementBernardo Perez Priego2021-06-181-0/+4
* soc/intel/{alderlake,tigerlake}: Fix typo in pmc.hWerner Zeh2021-06-171-1/+1
* soc/intel/alderlake/romstage: Refactor soc_memory_init_params functionSubrata Banik2021-06-171-46/+126
* soc/intel/alderlake/romstage: Update display UPDs based on InternalGfxSubrata Banik2021-06-162-39/+54
* soc/intel/alderlake: Make use of is_devfn_enabled() functionSubrata Banik2021-06-163-59/+25
* soc/intel/{common,alderlake}: Use generic name "Alderlake Platform"Sridhar Siricilla2021-06-111-3/+3
* soc/intel/alderlake/romstage: Drop ineffective FSP-M UPD `ChHashMask`Subrata Banik2021-06-081-2/+0
* soc/intel/alderlake: Set SaIpuEnable UPD according to devicetreeTim Wawrzynczak2021-06-081-0/+4
* soc/intel: Add Alder Lake's GT device IDSridhar Siricilla2021-06-081-0/+1
* soc/intel/alderlake: Correct TCSS XHCI Port status offsetSridhar Siricilla2021-06-081-2/+2
* cpu/x86: Default to PARALLEL_MP selectedKyösti Mälkki2021-06-071-1/+0
* soc/intel/adl: Add SKU specific power limits supportSumeet Pawnikar2021-06-073-2/+61
* soc/intel/alderlake: Update ACPI device ID of IOMMaulik V Vaghela2021-06-071-1/+1
* soc/intel: Drop unused lpss functionsFurquan Shaikh2021-06-071-23/+0
* soc/intel/alderlake: Set Base Addresses for TBT DMA remapping enginesSridhar Siricilla2021-06-071-0/+19
* soc/intel/alderlake: Add IDE-R and KT device into chipset.cbSubrata Banik2021-06-051-0/+2
* soc/intel/alderlake: Add PMC ACPI interfaceTim Wawrzynczak2021-06-041-0/+5
* soc/intel/alderlake: Add new memory parts for ADL boardsAmanda Huang2021-06-031-0/+2
* soc/intel/alderlake: Add placeholder SPD fileTim Wawrzynczak2021-05-301-0/+32
* soc/intel/alderlake: Update soundwire master countSugnan Prabhu S2021-05-261-1/+1
* soc/intel/alderlake: Add validity for TBT firmware authenticationJohn Zhao2021-05-261-0/+4
* soc/intel/alderlake: Fix SA_DEVFN_CPU_PCIE6_*Tim Wawrzynczak2021-05-251-2/+2
* soc/intel/common: Add Alder Lake device IDsSumeet R Pawnikar2021-05-211-0/+3
* soc/intel/alderlake: Add handling of GPIO_COM3 in gpio.aslMaulik V Vaghela2021-05-181-1/+10
* cpu/x86: Only include smm code if CONFIG_HAVE_SMI_HANDLER=yArthur Heymans2021-05-181-1/+0
* soc/intel/alderlake: mb/intel/sm: Add tcss codeDeepti Deshatty2021-05-183-17/+34
* soc/intel/alderlake: Update meminit code due to upd changes FSP 2147 onwardsBora Guvendik2021-05-161-5/+6
* vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2162_00Ronak Kanabar2021-05-161-8/+8
* soc/intel/alderlake: Update CPU and IGD Device IDsMaulik V Vaghela2021-05-141-0/+2
* soc/intel/alderlake: Add known GPIO virtual wire informationDeepti Deshatty2021-05-141-0/+27
* soc/intel/alderlake: Add known CPU Port IDs for GPIO communitiesDeepti Deshatty2021-05-142-0/+11
* soc/intel/alderlake: Add IOM PCR PIDDeepti Deshatty2021-05-141-0/+1
* src: Match array format in function declarations and definitionsPatrick Georgi2021-05-131-1/+1
* soc/intel/adl: Allow mainboard to fill CmdMirror and DqDqsRetrainingMaulik V Vaghela2021-05-102-0/+12
* soc/intel/{adl,tgl,jsl}: Enable power button smi after BS_CHIPS_EXITKane Chen2021-05-072-2/+13
* soc/intel/{adl,tgl,jsl}: Add smihandler_soc_disable_busmasterKane Chen2021-05-071-0/+8
* soc/intel/alderlake: Add CrashLog implementation for Intel ADLFrancois Toguo2021-05-067-1/+349
* soc/intel/alderlake: Add GPIO definition for CPU PCIe vGPIOMaulik V Vaghela2021-05-053-100/+237
* soc/intel/alderlake: remove duplicate PL2 overrideSumeet R Pawnikar2021-05-041-2/+0
* soc/intel/*: Update data types for variables holding PCH_DEVFN_* macrosTim Wawrzynczak2021-05-031-1/+1
* device: Switch pci_dev_is_wake_source to take pci_devfn_tTim Wawrzynczak2021-05-031-20/+8
* soc/intel/alderlake: Enable HWP CPPC support in CBravindr12021-05-031-0/+1
* soc/intel/alderlake: Fill FSPM UPDs for VT-d configurationMeera Ravindranath2021-05-031-3/+30
* soc/intel/alderlake: Use device ID from pci_devs header fileJohn Zhao2021-04-261-4/+5
* soc/intel/alderlake: Fix devices list in the DMAR DRHD structureJohn Zhao2021-04-261-17/+17
* soc/intel/alderlake: Add DPTF HIDs for Alder Lake SoCSumeet R Pawnikar2021-04-232-0/+19
* soc/intel/alderlake: Add enum for HDA audio configurationSugnan Prabhu S2021-04-222-4/+17
* soc/intel/alderlake and mb: Drop PchHdaAudioLink*Enable UPDs from chip.hFurquan Shaikh2021-04-222-15/+10
* soc/intel/alderlake: Drop unused `PrmrrSize` from devicetreeAngel Pons2021-04-211-10/+0
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