summaryrefslogtreecommitdiffstats
path: root/src/soc/intel/alderlake
Commit message (Expand)AuthorAgeFilesLines
* soc/amd,intel: Drop s3_resume parameter on FSP-S functionsKyösti Mälkki2021-02-092-4/+2
* soc/intel: Drop CID1 from GNVSKyösti Mälkki2021-02-081-4/+0
* soc/intel/alderlake: Increase VBT size to 9 KiBMaulik V Vaghela2021-02-071-0/+4
* drivers/intel/fsp2_0: Add support for MP services2 PPIAamir Bohra2021-02-061-1/+1
* intel: Rename config FSP_USES_MP_SERVICES_PPI to MP_SERVICES_PPIFurquan Shaikh2021-02-061-1/+1
* intel: Drop FSP_PEIM_TO_PEIM_INTERFACEFurquan Shaikh2021-02-061-1/+1
* soc/intel/alderlake: Refactor PCIE port configEric Lai2021-02-053-59/+75
* src: Remove unused <cbmem.h>Elyes HAOUAS2021-02-031-1/+0
* soc/intel/alderlake: Create separate Kconfig for CLKSRC and CLKREQSubrata Banik2021-02-012-5/+10
* soc/intel/*: drop incomplete and unneeded check for DMI SRLOCKMichael Niewöhner2021-01-311-15/+1
* soc/intel: Replace `SA_PCIEX_LENGTH` Kconfig optionsAngel Pons2021-01-301-1/+1
* soc/intel/alderlake: Remove pch.h from SoC directorySubrata Banik2021-01-305-14/+4
* device/Kconfig: Declare MMCONF symbols' type onceAngel Pons2021-01-291-1/+0
* arch/x86: Remove most C_ENV_BOOTBLOCK_SIZE limitsKyösti Mälkki2021-01-281-4/+0
* soc/intel/alderlake: Generate LP4x SPD files using gen_spd.goAmanda Huang2021-01-276-0/+179
* soc/intel: Move c-state resource defineMarc Jones2021-01-261-9/+0
* soc/intel/adl and mb/intel/adlrvp: Use the newly added meminit block driverFurquan Shaikh2021-01-253-236/+301
* soc/intel/{skl,cnl,xsp,icl,tgl,ehl,adl,jsl}: use common LPC mirroringMichael Niewöhner2021-01-252-25/+2
* ACPI: Add helpers for CBMEM_ID_POWER_STATEKyösti Mälkki2021-01-231-5/+3
* ELOG: Add const qualifier for chipset_power_stateKyösti Mälkki2021-01-231-2/+2
* soc/intel/alderlake: Adding Kconfig for ADL_M PCHVarshit Pandya2021-01-221-0/+8
* soc/intel/alderlake: Disable Internal Gfx based on SOC_INTEL_DISABLE_IGDSubrata Banik2021-01-211-5/+6
* soc/intel/*: drop broken LPC mmio codeMichael Niewöhner2021-01-201-15/+0
* ACPI GNVS: Drop most dev_count_cpu()Kyösti Mälkki2021-01-201-3/+0
* soc/intel/alderlake: Update PCH and CPU PCIe RP tableEric Lai2021-01-185-9/+55
* soc/intel/common: Move L1_substates_control to pcie_rp.hEric Lai2021-01-181-6/+2
* soc/intel: rename uart_max_indexMichael Niewöhner2021-01-121-1/+1
* soc/intel/alderlake: Add PCH ID 0x5182Subrata Banik2021-01-121-0/+1
* soc/intel/uart: Drop SoC callback `soc_uart_console_to_device`Furquan Shaikh2021-01-111-21/+5
* soc/intel/alderlake: Refactor SoC code to maintain CPU and PCH PCIE RPsSubrata Banik2021-01-104-14/+28
* soc/intel: Rename to soc_fill_gnvs()Kyösti Mälkki2021-01-101-1/+1
* ACPI: Drop redundant ChromeOS setup for GNVSKyösti Mälkki2021-01-101-11/+0
* ACPI: Drop redundant CONSOLE_CBMEM setup in GNVSKyösti Mälkki2021-01-101-4/+0
* soc/intel: Drop `dev` parameter from soc_get_gen_io_dec_range()Furquan Shaikh2021-01-081-2/+2
* soc/intel/alderlake: Update CPU microcode patch base address/sizeSubrata Banik2021-01-061-0/+11
* soc/intel/common: Move gfx.asl to drivers/intel/gmaMatt DeVillier2020-12-301-1/+1
* soc/intel: hook up new gpio device in the soc chipsMichael Niewöhner2020-12-302-0/+4
* soc/intel/alderlake: Update chipset.cb for TCSS and USBEric Lai2020-12-292-6/+96
* soc/intel/alderlake: Enable support for extended BIOS windowSubrata Banik2020-12-231-0/+7
* soc/intel/alderlake: Add SPI DMI Destination IDSubrata Banik2020-12-232-0/+13
* soc/intel/alderlake: Drop unreferenced devicetree settingsAngel Pons2020-12-141-8/+0
* soc/intel/common/dmi: Move DMI defines into DMI driver headerSrinidhi N Kaushik2020-12-091-3/+1
* soc/intel/alderlake: Align chipset.cb with pci_devs.hEric Lai2020-12-041-8/+9
* src/soc/intel/alderlake: Enable the PCH HDAV Sowmya2020-12-041-0/+3
* soc/intel/alderlake: Add initial chipset.cbTim Wawrzynczak2020-11-302-0/+71
* soc/intel: Configure P2SB before other PCH controllersFurquan Shaikh2020-11-291-2/+7
* soc/intel/alderlake: Add lp5_ccc_config to the board memory configurationSridhar Siricilla2020-11-292-0/+9
* soc/intel/alderlake: Update UART0 GPIO as per latest schematicsSubrata Banik2020-11-231-2/+2
* soc/intel/alderlake: Update DCACHE_BSP_STACK_SIZE and DCACHE_RAM_SIZESubrata Banik2020-11-231-3/+3
* soc/intel/alderlake: Fix overlapping memory address used for early GSPI2 and ...Bora Guvendik2020-11-221-1/+1
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-03 02:38:50 +0000