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path: root/src/soc/intel/alderlake
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* soc/intel/alderlake: Add eMMC device into chipset.cbKrishna Prasad Bhat2022-01-181-0/+2
* soc/intel/{adl,common}: Support alderlake host device id 0x4619Kane Chen2022-01-182-0/+2
* src: Remove unused <cbfs.h>Elyes HAOUAS2022-01-171-1/+0
* vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2511_04Nick Vaccaro2022-01-132-27/+27
* soc/intel/alderlake: Factor out A0 stepping workaroundAngel Pons2022-01-115-0/+104
* soc/intel/alderlake: Update the ADL-P SKU parameters for VR domainsCurtis Chen2022-01-103-35/+51
* soc/intel/alderlake: Hook up FSP-S CPU PCIe UPDsTim Wawrzynczak2022-01-071-0/+22
* soc/intel/alderlake: Check clkreq overlapKane Chen2022-01-071-1/+8
* soc/intel/alderlake: Add minimal ACPI support for PEG portsTim Wawrzynczak2022-01-062-0/+22
* soc/intel/alderlake: Add soc_get_cpu_rp_vw_idx() functionTim Wawrzynczak2022-01-061-0/+19
* soc/intel/alderlake: Fix GPIO reset mapping as per GPIO BWGSubrata Banik2022-01-061-23/+23
* src/soc/intel: Remove unused <delay.h>Elyes HAOUAS2022-01-051-1/+0
* soc/intel: Remove unused <string.h>Elyes HAOUAS2022-01-051-1/+0
* soc/intel/alderlake: Add option to make MRC log silentSubrata Banik2022-01-032-0/+4
* soc/intel/{adl,ehl,tgl}: Rename spi_protection_mode to mfg_modeSubrata Banik2022-01-022-3/+3
* src: Drop duplicated includesElyes HAOUAS2022-01-012-3/+0
* soc/intel/alderlake: Fix incorrect comment about debug consentSubrata Banik2021-12-301-1/+1
* soc/intel/alderlake: Add timestamp for cse_fw_syncSridhar Siricilla2021-12-231-1/+5
* soc/intel/alderlake: remove SOC_INTEL_COMMON_BLOCK_SMM_LOCK_GPIO_PADSScott Chao2021-12-221-1/+0
* soc/intel/common: Do not trigger crashlog on all resets by defaultCurtis Chen2021-12-201-7/+0
* soc/intel/alderlake: Implement function to map physical port to EC portMAULIK V VAGHELA2021-12-132-0/+33
* soc/intel/alderlake: Define soc_get_pcie_rp_typeTim Wawrzynczak2021-12-133-2/+62
* drivers/intel/mipi_camera: Add ACPI entry to provide silicon type infoSugnan Prabhu S2021-12-131-0/+6
* soc/intel/cse: config to enable oem key manifestRavindra N2021-12-101-1/+1
* soc/intel/alderlake: Fix value of SA_DEVFN_CPU_PCIE1_0Tim Wawrzynczak2021-12-091-1/+1
* soc/intel/alderlake: enable gpio lockingNick Vaccaro2021-12-072-0/+58
* soc/intel/alderlake: Add ADL-P 6+8+2 (28W) VR configCurtis Chen2021-12-061-0/+5
* soc/intel/alderlake: Add support for ADL-N CPU TypeUsha P2021-12-062-0/+12
* soc/intel: Move enum pcie_rp_type to intelblocks/pcie_rp.hTim Wawrzynczak2021-12-061-10/+5
* soc/intel/adl: Add override skip_cse_sub_part_update() for alderlakeKrishna Prasad Bhat2021-12-031-0/+6
* soc/intel/alderlake: Add support for ADL-N PCHUsha P2021-12-032-0/+11
* soc/intel/alderlake: Add the CnviDdrRfim configurationRonak Kanabar2021-12-032-0/+8
* soc/intel/alderlake: Add TDP to give correct VR configurationCurtis Chen2021-12-032-37/+38
* soc/intel/alderlake: Add Kconfigs for all PCH typesAngel Pons2021-12-022-7/+21
* soc/intel/common: Include Alder Lake-N device IDsUsha P2021-11-291-0/+6
* soc/intel/alderlake: Trigger cse_fw_sync before DRAM InitSridhar Siricilla2021-11-291-10/+4
* soc/intel/alderlake: Add ADLP 4+4+2 power configurationsCurtis Chen2021-11-254-3/+18
* soc/intel/adl: Modify SOC_INTEL_ALDERLAKE_DEBUG_CONSENT default valueKane Chen2021-11-251-4/+3
* soc/intel/alderlake: remove tmp bar assignment for cpu crashlogKane Chen2021-11-231-15/+2
* soc/intel/{adl,ehl,jsl,tgl}: Remove unused header `thermal.h`Subrata Banik2021-11-221-1/+0
* soc/intel/alderlake: Hook up common code for thermal configurationSubrata Banik2021-11-202-0/+12
* soc/intel/alderlake: Set `pch_thermal_trip` for Dynamic Thermal ShutdownSubrata Banik2021-11-201-0/+5
* soc/intel/alderlake: Update the VccIn Aux Imon IccMax for ADL-MBora Guvendik2021-11-191-0/+4
* soc/intel/alderlake: Add Acoustic noise mitigation UPDsWisley Chen2021-11-182-0/+38
* Revert "soc/intel/adl: Drop SGPM, RGPM and EGPM methods"Maulik V Vaghela2021-11-171-0/+41
* soc/intel/alderlake: Fix build failure with enabled CSE stitchingBernardo Perez Priego2021-11-151-17/+17
* Reland "vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main"Hsuan-ting Chen2021-11-151-0/+2
* soc/intel/alderlake: Disable VT-d for early siliconsMeera Ravindranath2021-11-151-0/+9
* Rename ECAM-specific MMCONF KconfigsShelley Chen2021-11-102-2/+2
* soc/intel/alderlake: Enable Intel FIVR RFI settingsWisley Chen2021-11-092-0/+42
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