summaryrefslogtreecommitdiffstats
path: root/src/soc/intel/braswell/chip.h
Commit message (Expand)AuthorAgeFilesLines
* soc/intel/braswell: Set GNVS DPTE via devicetreeAngel Pons2021-11-011-0/+2
* soc/intel/braswell/chip.h: Use `bool` typeAngel Pons2021-11-011-8/+8
* soc/intel/braswell,skylake: Drop logo parameters from devicetreeKyösti Mälkki2021-02-081-2/+0
* soc/intel/braswell: Clean up devicetree settingsAngel Pons2020-12-141-12/+0
* src/soc/intel: Drop unneeded empty linesElyes HAOUAS2020-09-211-1/+0
* treewide: Remove "this file is part of" linesPatrick Georgi2020-05-111-1/+0
* src: Remove not used 'include <smbios.h>'Elyes HAOUAS2020-05-011-1/+0
* soc/intel/braswell: Use SPDX for GPL-2.0-only filesAngel Pons2020-04-061-13/+2
* soc/intel/braswell: add ACPI backlight supportMatt DeVillier2020-04-021-0/+3
* soc/intel/braswell: Clean upAngel Pons2020-03-231-86/+83
* soc: Remove copyright noticesPatrick Georgi2020-03-181-3/+0
* soc/intel/braswell/chip.h: Include smbios.h for Type9 EntriesMichał Żygowski2020-03-091-0/+1
* soc/intel/braswell/chip.h: Add IGD_MEMSIZE_xxMBFrans Hendriks2019-10-031-0/+5
* devicetree: Remove duplicate chip_ops declarationsKyösti Mälkki2019-08-201-2/+0
* soc/intel/bsw: Move memory init values into `romstage.h`Nico Huber2019-05-071-3/+0
* soc/intel/braswell: add default option to use public FSPMatt DeVillier2019-05-031-5/+0
* soc/intel/braswell: Correct serial IRQ supportFrans Hendriks2019-04-041-0/+4
* soc/intel/braswell: add USB2 PHY PERPORTRXISET UPDKevin Chiu2017-09-081-0/+5
* soc/intel/braswell: Add I2C clock config optionsDivagar Mohandass2017-09-081-0/+7
* soc/intel/braswell: Fix most of the issues detected by checkpatchLee Leahy2017-03-171-1/+1
* soc/intel/braswell: Fix spacing issues detected by checkpatchLee Leahy2017-03-171-6/+6
* soc/braswell: Add interface to program USB2_COMPBG registershkim2016-01-281-0/+20
* Strago: Enable CA MirrorShobhit Srivastava2016-01-281-0/+1
* soc/braswell: Disable SD card detect simulation in FSPDivya Sasidharan2016-01-281-0/+1
* soc/braswell: Fix DSP clockfdurairx2016-01-281-2/+6
* tree: drop last paragraph of GPL copyright headerPatrick Georgi2015-10-311-4/+0
* Braswell: Modify CB to accomodate new FSPv83Subrata Banik2015-10-111-2/+0
* fsp1_1: provide binding to UEFI versionAaron Durbin2015-09-101-1/+1
* intel/braswell: fix buildJenny TC2015-07-291-0/+3
* BCRD2: Enable PMIC SVID configJenny TC2015-07-291-2/+3
* Braswell: Update to end of June.Lee Leahy2015-07-061-0/+1
* Braswell: Add Braswell SOC supportLee Leahy2015-06-251-49/+97
* Remove address from GPLv2 headersPatrick Georgi2015-05-281-1/+1
* Braswell: Use Baytrail as Comparison BaseLee Leahy2015-05-231-0/+95
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-16 21:50:52 +0000