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path: root/src/soc/intel/braswell/cpu.c
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* cpu/x86/lapic: Move LAPIC configuration to MP initKyösti Mälkki2022-02-051-3/+0
* soc/intel/braswell: use mp_cpu_bus_initFelix Held2021-10-221-3/+2
* cpu/x86/mp_init: move printing of failure message into mp_init_with_smmFelix Held2021-10-221-2/+2
* cpu/x86/mp_init: use cb_err as mp_init_with_smm return typeFelix Held2021-10-211-1/+2
* cpu/x86/mpinit: Serialize microcode updates for HT threadsPatrick Rudolph2021-01-151-1/+1
* src/soc/intel: Drop unneeded empty linesElyes HAOUAS2020-09-211-1/+0
* soc/intel/braswell: Drop some BIOS_SPEW printk'sAngel Pons2020-07-091-4/+0
* sb,soc/intel: Replace smm_southbridge_enable_smi()Kyösti Mälkki2020-06-161-1/+6
* treewide: Remove "this file is part of" linesPatrick Georgi2020-05-111-1/+0
* src: Remove unused 'include <cpu/x86/cache.h>'Elyes HAOUAS2020-05-011-1/+0
* soc/intel/braswell: Use SPDX for GPL-2.0-only filesAngel Pons2020-04-061-13/+2
* soc/intel/braswell: Clean upAngel Pons2020-03-231-23/+19
* soc: Remove copyright noticesPatrick Georgi2020-03-181-3/+0
* src/soc/intel: Remove unused <stdlib.h>Elyes HAOUAS2019-12-191-1/+0
* intel/smm: Provide common smm_relocation_paramsKyösti Mälkki2019-11-221-9/+0
* intel/braswell: Use smm_subregion()Kyösti Mälkki2019-08-281-24/+28
* soc/intel: Rename some SMM support functionsKyösti Mälkki2019-08-151-3/+4
* cpu/x86: Separate save_state struct headersKyösti Mälkki2019-08-131-0/+1
* arch/x86: Change smm_subregion() prototypeKyösti Mälkki2019-08-081-2/+2
* cpu/x86/smm: Promote smm_subregion()Kyösti Mälkki2019-08-071-1/+0
* src/soc/intel/braswell/cpu.c: Set up local APICFrans Hendriks2019-03-041-0/+4
* cpu/intel/common: decouple IA32_FEATURE_CONTROL lock from set_vmx()Matt DeVillier2018-12-201-1/+1
* soc/intel/braswell: add vmx support via CPU_INTEL_COMMONMatt DeVillier2018-11-161-0/+4
* src: Remove unneeded whitespaceElyes HAOUAS2018-10-231-2/+2
* src: Move common IA-32 MSRs to <cpu/x86/msr.h>Elyes HAOUAS2018-10-111-1/+1
* src: Fix MSR_PKG_CST_CONFIG_CONTROL register nameElyes HAOUAS2018-10-051-1/+1
* cpu/x86/mtrr.h: Rename MSR SMRR_PHYS_x to IA32_SMRR_PHYSxArthur Heymans2018-07-241-2/+2
* soc/intel/braswell: Get rid of device_tElyes HAOUAS2018-06-041-2/+2
* Constify struct cpu_device_id instancesJonathan Neuschäfer2017-11-231-1/+1
* cpu/x86/mp_init: remove adjust_cpu_apic_entry()Aaron Durbin2017-09-111-7/+0
* soc/intel/braswell: Fix most of the issues detected by checkpatchLee Leahy2017-03-171-2/+1
* soc/intel/braswell: convert to using common MP and SMM initAaron Durbin2016-05-061-191/+90
* cpu/x86/mp_init: remove unused callback argumentsAaron Durbin2016-05-021-10/+10
* x86 chipsets: utilize x86_setup_mtrrs_with_detect()Aaron Durbin2016-03-081-2/+1
* soc/braswell: Add CPUID for D0 steppingDivya Sasidharan2016-01-141-0/+1
* tree: drop last paragraph of GPL copyright headerPatrick Georgi2015-10-311-4/+0
* FSP 1.1: Move common FSP codeLee Leahy2015-10-271-1/+1
* cpu/mtrr.h: Fix macro names for MTRR registersAlexandru Gagniuc2015-10-151-3/+3
* intel/braswell: allow dirty cache line evictions for SMRAM to stickChiranjeevi Rapolu2015-08-291-0/+10
* Braswell: Update to end of June.Lee Leahy2015-07-061-1/+52
* Braswell: Add Braswell SOC supportLee Leahy2015-06-251-73/+43
* Remove address from GPLv2 headersPatrick Georgi2015-05-281-1/+1
* Braswell: Use Baytrail as Comparison BaseLee Leahy2015-05-231-0/+309
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