coreboot.git - Coreboot firmware sources

	Commit message (Expand)	Author	Age	Files	Lines
*	soc/intel/broadwell: Move PCH code into pch subdir	Angel Pons	2020-10-30	1	-325/+0
*	src/soc/intel: Drop unneeded empty lines	Elyes HAOUAS	2020-09-21	1	-1/+0
*	treewide: Remove "this file is part of" lines	Patrick Georgi	2020-05-11	1	-1/+0
*	soc/intel/broadwell: Use SPDX for GPL-2.0-only files	Angel Pons	2020-04-06	1	-13/+2
*	soc: Remove copyright notices	Patrick Georgi	2020-03-18	1	-1/+0
*	src/soc/intel: Remove unused <stdlib.h>	Elyes HAOUAS	2019-12-19	1	-1/+0
*	sb,soc/intel: Reduce preprocessor use with ME debugging	Kyösti Mälkki	2019-11-08	1	-3/+3
*	arch/io.h: Drop unnecessary include	Kyösti Mälkki	2019-03-04	1	-1/+0
*	device/pci: Fix PCI accessor headers	Kyösti Mälkki	2019-03-01	1	-0/+1
*	soc: Remove useless include <device/pci_ids.h>	Elyes HAOUAS	2018-12-19	1	-1/+0
*	broadwell/me: Fix out-of-bounds array access error	Evan Lojewski	2016-05-04	1	-13/+37
*	tree: drop last paragraph of GPL copyright header	Patrick Georgi	2015-10-31	1	-4/+0
*	Remove address from GPLv2 headers	Patrick Georgi	2015-05-21	1	-1/+1
*	broadwell: Change all SoC headers to <soc/headername.h> system	Julius Werner	2015-04-07	1	-2/+2
*	broadwell: Fix building with USE=quiet-cb	Duncan Laurie	2015-04-04	1	-6/+6
*	broadwell: me: Fix typo and add missing phase state	Duncan Laurie	2015-04-02	1	-1/+5
*	broadwell: Read and save HSIO version from ME in romstage	Duncan Laurie	2015-03-27	1	-0/+36
*	intel/broadwell: Spelling fixes	Martin Roth	2014-12-08	1	-1/+1
*	broadwell: ACPI, romstage, and other updates	Duncan Laurie	2014-10-22	1	-0/+3
*	broadwell: add new intel SOC	Duncan Laurie	2014-10-22	1	-0/+278