coreboot.git - Coreboot firmware sources

	Commit message (Expand)	Author	Age	Files	Lines
*	soc/intel/broadwell: Merge `device_nvs.asl` into `globalnvs.asl`	Angel Pons	2020-11-04	2	-39/+32
*	soc/intel/broadwell: Include EC and IRQ links ACPI early	Angel Pons	2020-11-04	1	-2/+4
*	soc/intel/broadwell/pch: Use common PCIe ACPI code	Angel Pons	2020-11-04	3	-214/+1
*	soc/intel/broadwell/pch/acpi: Add PCIe register offsets	Angel Pons	2020-11-04	1	-0/+6
*	soc/intel/broadwell: Use common irqlinks.asl	Angel Pons	2020-11-04	2	-474/+1
*	soc/intel/broadwell/pch/acpi/irqlinks.asl: Add missing IRQs	Angel Pons	2020-11-04	1	-8/+8
*	soc/intel/broadwell: Align ACPI with Haswell/Lynxpoint	Angel Pons	2020-11-04	3	-11/+3
*	soc/intel/broadwell: Relocate PCH ACPI files	Angel Pons	2020-11-03	15	-0/+2309
*	soc/intel/broadwell: Drop reg-script to finalize PCH	Angel Pons	2020-10-30	1	-20/+12
*	soc/intel/broadwell: Relocate PCH finalisation code	Angel Pons	2020-10-30	2	-0/+52
*	soc/intel/broadwell: Move PCH code into pch subdir	Angel Pons	2020-10-30	25	-0/+6160
*	soc/intel/broadwell: Separate PCH in devicetree	Angel Pons	2020-10-30	1	-0/+78