coreboot.git - Coreboot firmware sources

	Commit message (Expand)	Author	Age	Files	Lines
*	soc/intel/broadwell: Implement postcar stage	Arthur Heymans	2018-12-05	1	-318/+0
*	cpu/*/car: fix ancient URL explaining XIP range run-time calculation	Stefan Tauner	2018-09-18	1	-1/+1
*	x86/car: Replace reference of copy_and_run location	Kyösti Mälkki	2018-06-27	1	-1/+1
*	Use more secure HTTPS URLs for coreboot sites	Paul Menzel	2017-06-07	1	-1/+1
*	src/soc: Capitalize CPU, ACPI, RAM and ROM	Elyes HAOUAS	2016-07-31	1	-1/+1
*	intel/broadwell: Remove old USBDEBUG backup store in CAR	Kyösti Mälkki	2016-06-19	1	-13/+0
*	intel cache_as_ram: Fix typo in comment	Kyösti Mälkki	2016-06-18	1	-1/+1
*	Fix some cbmem.h includes	Kyösti Mälkki	2016-06-17	1	-1/+0
*	tree: drop last paragraph of GPL copyright header	Patrick Georgi	2015-10-31	1	-4/+0
*	cpu/mtrr.h: Fix macro names for MTRR registers	Alexandru Gagniuc	2015-10-15	1	-19/+19
*	Intel: Remove CACHE_MRC_BIN - 'selected' everywhere in Kconfig	Martin Roth	2015-08-25	1	-4/+0
*	x86: Drop -Wa,--divide	Stefan Reinauer	2015-07-07	1	-2/+2
*	Remove empty lines at end of file	Elyes HAOUAS	2015-06-08	1	-1/+0
*	Remove address from GPLv2 headers	Patrick Georgi	2015-05-21	1	-1/+1
*	Broadwell: Pass TSC value to romstage_main	Lee Leahy	2015-04-04	1	-0/+6
*	broadwell: Preparations for building	Marc Jones	2014-12-31	1	-1/+0
*	broadwell: add new intel SOC	Duncan Laurie	2014-10-22	1	-0/+336