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* pciexp_device: Rewrite LTR configurationNico Huber2021-03-151-6/+4
* device: Give `pci_ops.set_L1_ss_latency` a proper nameNico Huber2021-03-121-2/+2
* soc/intel/broadwell/pch: Rename USB filesAngel Pons2021-03-053-3/+3
* soc/intel/broadwell/pch: Use Lynx Point smbus.cAngel Pons2021-03-054-79/+1
* soc/intel: Guard macro parameters in pm.hAngel Pons2021-03-031-2/+2
* soc/intel/broadwell: Use ctdp.asl from HaswellAngel Pons2021-03-012-219/+1
* soc/intel/broadwell: Use cbmem_recovery()Kyösti Mälkki2021-02-231-7/+8
* soc/intel/{baytrail,braswell,broadwell}: Remove unused <string.h>Elyes HAOUAS2021-02-163-3/+0
* vc/google/chromeos: Always use CHROMEOS_RAMOOPS_DYNAMICKyösti Mälkki2021-02-161-3/+0
* soc/inteL/broadwell: Move select CHROMEOS_RAMOOPS_DYNAMICKyösti Mälkki2021-02-162-4/+3
* ACPI: Add acpi_reset_gnvs_for_wake()Kyösti Mälkki2021-02-162-31/+14
* soc/intel: Remove unused <console/console.h>Elyes HAOUAS2021-02-151-1/+0
* soc/intel/broadwell/pch: Use Lynxpoint GPIO codeAngel Pons2021-02-152-136/+3
* broadwell boards: Switch to Lynxpoint GPIO headersAngel Pons2021-02-152-13/+8
* soc/intel/broadwell/pch: Prepare to drop `gpio.h`Angel Pons2021-02-156-177/+8
* soc/intel/broadwell/pch: Rename GPIO identifiersAngel Pons2021-02-153-15/+15
* intel/broadwell,lynxpoint: Use HPTS() for HPET visibilityKyösti Mälkki2021-02-131-11/+1
* soc/intel/broadwell: Use southbridge common RCBAAngel Pons2021-02-126-22/+8
* ACPI: Move PICM declarationKyösti Mälkki2021-02-111-2/+0
* sb,soc/intel: Drop OSYS from GNVSKyösti Mälkki2021-02-112-2/+2
* mainboards: Drop PWRS from GNVSKyösti Mälkki2021-02-112-2/+2
* src: Remove unused <arch/cpu.h>Elyes HAOUAS2021-02-111-1/+0
* soc/intel/broadwell: Remove _ADR from SerialIO ACPI devicesAngel Pons2021-02-111-8/+0
* soc/intel/broadwell/pch: Simplify PCI RMW operationsAngel Pons2021-02-103-40/+33
* soc/intel/broadwell: Use common MADT codeAngel Pons2021-02-103-49/+1
* soc/intel/broadwell/pch: Drop `acpi_sci_irq` functionAngel Pons2021-02-104-33/+2
* soc/intel/{baytrail,broadwell}: Add missing <cbmem.h>Angel Pons2021-02-081-0/+1
* soc/intel/broadwell/include/soc/me.h: Clean includesElyes HAOUAS2021-02-071-1/+1
* soc/intel/broadwell: Use common {DMI,EP,MCH}BAR accessorsAngel Pons2021-02-076-14/+17
* soc/intel/broadwell: Convert to ASL 2.0 syntaxElyes HAOUAS2021-02-071-7/+8
* soc/intel/broadwell: Conditionally skip PRE_GRAPHICS_DELAYKyösti Mälkki2021-02-062-15/+0
* soc/intel/broadwell: Convert some CONFIG(CHROMEOS) preprocessorKyösti Mälkki2021-02-051-5/+1
* soc/intel/broadwell/pch/lpc.c: Program GEN_PMCON_3 in one writeAngel Pons2021-02-051-13/+9
* src: Remove unused <cbmem.h>Elyes HAOUAS2021-02-033-3/+0
* soc/intel/broadwell/gma.c: Add missing `break` in switchAngel Pons2021-02-011-0/+1
* src: Remove unused <cpu/x86/smm.h>Elyes HAOUAS2021-02-012-2/+0
* soc/intel/broadwell/pch/sata.c: Don't enable Bus MasterAngel Pons2021-02-011-3/+2
* soc/intel/broadwell/pch: Drop some `config_of` usesAngel Pons2021-01-302-14/+24
* soc/intel/broadwell: Move `ramstage.c` to PCH scopeAngel Pons2021-01-303-1/+1
* soc/intel/broadwell: Make `broadwell_init_pre_device` staticAngel Pons2021-01-303-8/+5
* soc/intel/broadwell: Define and use MMCONF_BUS_NUMBERAngel Pons2021-01-306-20/+26
* soc/intel/broadwell: Use common SMBus codeAngel Pons2021-01-303-50/+3
* soc/intel/{baytrail,broadwell} Fix building with refcode blobsAngel Pons2021-01-301-6/+6
* soc/amd,intel: Drop leftover GNVS includesKyösti Mälkki2021-01-302-2/+0
* soc/intel: Drop CMEM from GNVSKyösti Mälkki2021-01-291-1/+1
* soc/intel/baytrail,broadwell: Use resume_from_stage_cache()Kyösti Mälkki2021-01-291-13/+5
* ACPI: Separate ChromeOS NVS in ASLKyösti Mälkki2021-01-281-4/+0
* ACPI: Declare GNVS variables globallyKyösti Mälkki2021-01-282-12/+0
* ACPI: Separate device_nvs_tKyösti Mälkki2021-01-278-68/+59
* sb,soc/intel: Refactor power_on_after_fail optionKyösti Mälkki2021-01-261-13/+15
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