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path: root/src/soc/intel/cannonlake/acpi/southbridge.asl
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* soc/intel: Rename pcr.asl to pch_pcr.aslSubrata Banik2023-07-131-1/+1
* soc/intel/cannonlake: Switch to runtime generation of Intel Power EngineTim Wawrzynczak2021-09-101-3/+0
* soc/intel/cannonlake: Use new IRQ moduleTim Wawrzynczak2021-06-291-3/+0
* soc/intel: Include gfx.asl from northbridgeAngel Pons2021-03-011-3/+0
* soc/intel/common: Move gfx.asl to drivers/intel/gmaMatt DeVillier2020-12-301-1/+1
* soc/intel/common/acpi,mb/*: replace the two obsolete LPID with PEPDMichael Niewöhner2020-11-201-2/+2
* soc/intel/common/block/acpi: Factor out common gfx.aslSubrata Banik2020-10-081-1/+1
* soc/intel/common/block/acpi: Factor out common ish.aslSubrata Banik2020-10-051-1/+1
* soc/intel/common/block/acpi: Factor out common smbus.aslSubrata Banik2020-10-051-1/+1
* soc/intel/common/block/acpi: Factor out common pch_glan.aslSubrata Banik2020-10-051-2/+2
* soc/intel/cnl: Add ACPI support for PMC core OS driverMichael Niewöhner2020-09-141-0/+3
* treewide: Remove "this file is part of" linesPatrick Georgi2020-05-111-1/+0
* treewide: replace GPLv2 long form headers with SPDX headerPatrick Georgi2020-05-061-12/+1
* treewide: Move "is part of the coreboot project" line in its own commentPatrick Georgi2020-05-061-2/+1
* soc: Remove copyright noticesPatrick Georgi2020-03-181-2/+0
* soc/intel/cannonlake: Add gfx.asl fileMathew King2019-12-021-0/+3
* soc/intel/{apl,cnl,dnv,icl,skl}: Move lpc.asl into common/block/acpiSubrata Banik2019-11-011-1/+1
* soc/intel/cannonlake: Remove unused header files from southbridge.aslAamir Bohra2019-07-131-5/+0
* coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner2019-03-081-1/+1
* soc/intel/cnl/acpi: add ish ACPI deviceJett Rink2019-03-041-0/+3
* soc/intel/cannonlake: Make static IRQ mapping for CNP PCH pci devicesSubrata Banik2018-11-151-3/+0
* mb/{intel/google}: Move CNVi ASL entry from static DSDT to dynamic SSDT gener...Subrata Banik2018-11-071-3/+0
* soc/intel/cannonlake: Add CNP PCH-H gpio pin definitionspraveen hodagatta pranesh2018-10-171-0/+4
* soc/intel/cannonlake: Add PCIE ASL entrySubrata Banik2018-10-091-0/+3
* soc/intel/cannonlake: Make correct IRQ mapping for CNL SA and PCH PCI devicesSubrata Banik2018-10-091-0/+7
* soc/intel/cannonlake: Add ACPI entry for LANLijian Zhao2018-09-281-1/+4
* soc/intel/cannonlake: Fix comment errors for SMBUSLijian Zhao2018-08-301-1/+1
* soc/intel/cannonlake: Clear EMMC timeout registerLijian Zhao2018-02-221-3/+3
* soc/intel/cannonlake: Use common PCR ASLLijian Zhao2018-02-161-1/+1
* src/soc/intel/cannonlake: Add _PRW for CNViBora Guvendik2017-12-131-0/+3
* soc/intel/cannonlake: Add all the SOC level DSDT tablesLijian Zhao2017-10-051-0/+18
* soc/intel/cannonlake: add initial ASL methods for SCS, GPIOBora Guvendik2017-10-031-0/+9
* soc/intel/cannonlake: Add PCIE IRQsBora Guvendik2017-09-191-0/+20
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