| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | soc/intel/common: Add SOC specific function to get XHCI USB info | Karthikeyan Ramasubramanian | 2019-07-19 | 1 | -13/+1 |
| * | soc/intel/cannonlake: Add support to log XHCI wake events | Paul Fagerburg | 2019-07-02 | 1 | -2/+15 |
| * | soc/intel/cannonlake: Fix GEN_PMCON bit checks | Furquan Shaikh | 2019-03-15 | 1 | -3/+3 |
| * | soc/intel/cannonlake: Add support for logging wake source in SMM | V Sowmya | 2019-03-07 | 1 | -0/+7 |
| * | soc/intel/cannonlake: complete rename of TCO2_STS_SECOND_TO | Patrick Georgi | 2019-01-10 | 1 | -1/+1 |
| * | soc/intel/cannonlake: Add chipset event logging | Duncan Laurie | 2019-01-08 | 1 | -0/+125 |
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index : coreboot.git | |
| Coreboot firmware sources | coreboot |
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