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path:
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src
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intel
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cannonlake
/
fsp_params.c
Commit message (
Expand
)
Author
Age
Files
Lines
*
treewide: Remove "this file is part of" lines
Patrick Georgi
2020-05-11
1
-1
/
+0
*
soc/intel/cannonlake: Use SPDX for GPL-2.0-only files
Angel Pons
2020-04-06
1
-13
/
+2
*
soc: Remove copyright notices
Patrick Georgi
2020-03-18
1
-1
/
+0
*
soc/intel/cannonlake: Set correct serirq mode
Jeremy Soller
2020-03-17
1
-0
/
+4
*
soc/intel/cannonlake: Plumb TetonGlacierMode into dt
Edward O'Callaghan
2020-02-28
1
-0
/
+3
*
soc/intel/{cnl,icl}: Avoid static 8254 clock gating on S3 resume
Subrata Banik
2020-02-26
1
-1
/
+1
*
{drivers,soc}/intel/fsp2_0: Move chipset specific logo handling to SoC
Wim Vervoorn
2019-12-19
1
-0
/
+7
*
soc/intel/cannonlake: Disable USB2 PHY Power gating
Surendranath Gurivireddy
2019-11-27
1
-0
/
+3
*
soc/intel/cannonlake: set FSP param to enable or skip GOP
Michael Niewöhner
2019-10-30
1
-0
/
+6
*
soc/intel/cannonlake: Fix FSP UPDs settings with disabled GBE
Kane Chen
2019-10-22
1
-1
/
+12
*
soc/intel: Replace config_of_path() with config_of_soc()
Kyösti Mälkki
2019-10-02
1
-2
/
+2
*
soc/intel/cnl: Remove unnecessary FSP UPD “PchPwrOptEnable” usage
Subrata Banik
2019-09-12
1
-1
/
+0
*
soc/intel/cannonlake: Add config for sata devslp pad reset configuration
Aamir Bohra
2019-09-12
1
-0
/
+5
*
soc/intel/cannonlake: Allow coreboot to handle SPI lockdown
Subrata Banik
2019-09-09
1
-8
/
+6
*
soc/intel/cannonlake: Add ability to disable Heci1
Bora Guvendik
2019-09-09
1
-0
/
+3
*
soc/intel/cannonlake: Add config to disable display audio codec
Aamir Bohra
2019-08-26
1
-0
/
+1
*
soc/intel/cnl: Add provision to configure SD controller write protect pin
Aamir Bohra
2019-08-20
1
-0
/
+3
*
soc/intel/{cnl,icl}: Add support to get LPSS controllers list from SOC
Aamir Bohra
2019-08-05
1
-0
/
+8
*
soc/intel/cannonlake: Disable ACPI PM timer to reduce S0ix power usage
Subrata Banik
2019-08-02
1
-0
/
+3
*
soc/intel/cannonlake: Allow coreboot to handle required chipset lockdown
Subrata Banik
2019-07-30
1
-0
/
+34
*
soc/intel/cannonlake: Correct the data type of serial_io_dev
Aamir Bohra
2019-07-29
1
-1
/
+1
*
soc/intel: Use config_of_path(SA_DEVFN_ROOT)
Kyösti Mälkki
2019-07-18
1
-9
/
+4
*
soc/intel/cnl: Sync CONFIG_LPSS_UART_FOR_CONSOLE with FSP
Nico Huber
2019-07-13
1
-0
/
+3
*
soc/intel: Replace uses of dev_find_slot()
Kyösti Mälkki
2019-07-04
1
-8
/
+8
*
soc/intel/cannonlake: fix use of legacy 8254 timer
Matt DeVillier
2019-06-28
1
-0
/
+4
*
soc/intel/cannonlake: Configure SPI CS parameters in FSP UPD.
Tim Wawrzynczak
2019-05-20
1
-0
/
+43
*
mb/google/sarien: Disable S5 wake on LAN by default
Eric Lai
2019-05-01
1
-0
/
+4
*
soc/{amd,intel}/chip: Use local include for chip.h
Elyes HAOUAS
2019-04-26
1
-1
/
+2
*
soc/intel/cannonlake: Add null reference check for Cnvi and Xdci
Aamir Bohra
2019-04-23
1
-5
/
+14
*
Revert "soc/intel/cannonlake: Enable coreboot MP PPI service for WHL/CML"
Lijian Zhao
2019-04-22
1
-5
/
+0
*
soc/intel/cannonlake: Enable coreboot MP PPI service for WHL/CML
Subrata Banik
2019-04-16
1
-0
/
+5
*
Replace remaining IS_ENABLED(CONFIG_*) with CONFIG()
Nico Huber
2019-04-08
1
-2
/
+2
*
soc/intel/cannonlake: Add FSP UPD to unlock GPIO pads in devicetree
Krishna Prasad Bhat
2019-04-01
1
-0
/
+3
*
soc/intel/cannonlake: Ignore GBE LTR
Lijian Zhao
2019-03-29
1
-0
/
+12
*
soc/intel/cannonlake: Configure voltage margining policies
Krzysztof Sywula
2019-03-27
1
-1
/
+8
*
soc/intel/cannonlake: Assign FSP UPDs for HPD and Data/CLK of DDI ports
Krishna Prasad Bhat
2019-03-21
1
-0
/
+15
*
soc/intel/cannonlake: Fix return values for get_param_value
Furquan Shaikh
2019-03-20
1
-3
/
+9
*
soc/intel/cannonlake: Add required FSP UPD changes for CML
Subrata Banik
2019-03-16
1
-28
/
+70
*
coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
Julius Werner
2019-03-08
1
-1
/
+1
*
soc/intel/cannonlake: Add a config for configuring SD_VDD1_PWR_EN#
Rizwan Qureshi
2019-02-27
1
-2
/
+5
*
soc/intel/cannonlake: Add support for setting FSP-S PcieRpHotPlug from device...
Jeremy Soller
2019-02-22
1
-0
/
+2
*
src/soc/intel/cannonlake: Add PsysPmax setting
Gaggery Tsai
2019-02-21
1
-0
/
+7
*
soc/intel/cannonlake: Configure serial debug uart
Ronak Kanabar
2019-02-13
1
-0
/
+3
*
soc/intel/cannonlake: Provide interface to update TCC offset
John Su
2019-01-14
1
-0
/
+4
*
soc/intel/cannonlake: Add FSP UPD for minimum assertion width
Duncan Laurie
2019-01-08
1
-0
/
+10
*
soc/intel/cannonlake: Enable CNVi based on devicetree
Maulik V Vaghela
2019-01-01
1
-0
/
+4
*
soc/intel/cannonlake: SATA and DMI power optimize
Lijian Zhao
2018-12-19
1
-0
/
+4
*
soc/intel/cannonlake: Add Acoustic features
Lijian Zhao
2018-12-19
1
-0
/
+11
*
soc/intel/cannonlake: Add options for pcie ltr
Lijian Zhao
2018-11-17
1
-0
/
+2
*
soc/intel/cannonlake: Remove depreciated UPD selection
Lijian Zhao
2018-11-05
1
-5
/
+0
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