summaryrefslogtreecommitdiffstats
path: root/src/soc/intel/cannonlake/fsp_params.c
Commit message (Expand)AuthorAgeFilesLines
* treewide: Remove "this file is part of" linesPatrick Georgi2020-05-111-1/+0
* soc/intel/cannonlake: Use SPDX for GPL-2.0-only filesAngel Pons2020-04-061-13/+2
* soc: Remove copyright noticesPatrick Georgi2020-03-181-1/+0
* soc/intel/cannonlake: Set correct serirq modeJeremy Soller2020-03-171-0/+4
* soc/intel/cannonlake: Plumb TetonGlacierMode into dtEdward O'Callaghan2020-02-281-0/+3
* soc/intel/{cnl,icl}: Avoid static 8254 clock gating on S3 resumeSubrata Banik2020-02-261-1/+1
* {drivers,soc}/intel/fsp2_0: Move chipset specific logo handling to SoCWim Vervoorn2019-12-191-0/+7
* soc/intel/cannonlake: Disable USB2 PHY Power gatingSurendranath Gurivireddy2019-11-271-0/+3
* soc/intel/cannonlake: set FSP param to enable or skip GOPMichael Niewöhner2019-10-301-0/+6
* soc/intel/cannonlake: Fix FSP UPDs settings with disabled GBEKane Chen2019-10-221-1/+12
* soc/intel: Replace config_of_path() with config_of_soc()Kyösti Mälkki2019-10-021-2/+2
* soc/intel/cnl: Remove unnecessary FSP UPD “PchPwrOptEnable” usageSubrata Banik2019-09-121-1/+0
* soc/intel/cannonlake: Add config for sata devslp pad reset configurationAamir Bohra2019-09-121-0/+5
* soc/intel/cannonlake: Allow coreboot to handle SPI lockdownSubrata Banik2019-09-091-8/+6
* soc/intel/cannonlake: Add ability to disable Heci1Bora Guvendik2019-09-091-0/+3
* soc/intel/cannonlake: Add config to disable display audio codecAamir Bohra2019-08-261-0/+1
* soc/intel/cnl: Add provision to configure SD controller write protect pinAamir Bohra2019-08-201-0/+3
* soc/intel/{cnl,icl}: Add support to get LPSS controllers list from SOCAamir Bohra2019-08-051-0/+8
* soc/intel/cannonlake: Disable ACPI PM timer to reduce S0ix power usageSubrata Banik2019-08-021-0/+3
* soc/intel/cannonlake: Allow coreboot to handle required chipset lockdownSubrata Banik2019-07-301-0/+34
* soc/intel/cannonlake: Correct the data type of serial_io_devAamir Bohra2019-07-291-1/+1
* soc/intel: Use config_of_path(SA_DEVFN_ROOT)Kyösti Mälkki2019-07-181-9/+4
* soc/intel/cnl: Sync CONFIG_LPSS_UART_FOR_CONSOLE with FSPNico Huber2019-07-131-0/+3
* soc/intel: Replace uses of dev_find_slot()Kyösti Mälkki2019-07-041-8/+8
* soc/intel/cannonlake: fix use of legacy 8254 timerMatt DeVillier2019-06-281-0/+4
* soc/intel/cannonlake: Configure SPI CS parameters in FSP UPD.Tim Wawrzynczak2019-05-201-0/+43
* mb/google/sarien: Disable S5 wake on LAN by defaultEric Lai2019-05-011-0/+4
* soc/{amd,intel}/chip: Use local include for chip.hElyes HAOUAS2019-04-261-1/+2
* soc/intel/cannonlake: Add null reference check for Cnvi and XdciAamir Bohra2019-04-231-5/+14
* Revert "soc/intel/cannonlake: Enable coreboot MP PPI service for WHL/CML"Lijian Zhao2019-04-221-5/+0
* soc/intel/cannonlake: Enable coreboot MP PPI service for WHL/CMLSubrata Banik2019-04-161-0/+5
* Replace remaining IS_ENABLED(CONFIG_*) with CONFIG()Nico Huber2019-04-081-2/+2
* soc/intel/cannonlake: Add FSP UPD to unlock GPIO pads in devicetreeKrishna Prasad Bhat2019-04-011-0/+3
* soc/intel/cannonlake: Ignore GBE LTRLijian Zhao2019-03-291-0/+12
* soc/intel/cannonlake: Configure voltage margining policiesKrzysztof Sywula2019-03-271-1/+8
* soc/intel/cannonlake: Assign FSP UPDs for HPD and Data/CLK of DDI portsKrishna Prasad Bhat2019-03-211-0/+15
* soc/intel/cannonlake: Fix return values for get_param_valueFurquan Shaikh2019-03-201-3/+9
* soc/intel/cannonlake: Add required FSP UPD changes for CMLSubrata Banik2019-03-161-28/+70
* coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner2019-03-081-1/+1
* soc/intel/cannonlake: Add a config for configuring SD_VDD1_PWR_EN#Rizwan Qureshi2019-02-271-2/+5
* soc/intel/cannonlake: Add support for setting FSP-S PcieRpHotPlug from device...Jeremy Soller2019-02-221-0/+2
* src/soc/intel/cannonlake: Add PsysPmax settingGaggery Tsai2019-02-211-0/+7
* soc/intel/cannonlake: Configure serial debug uartRonak Kanabar2019-02-131-0/+3
* soc/intel/cannonlake: Provide interface to update TCC offsetJohn Su2019-01-141-0/+4
* soc/intel/cannonlake: Add FSP UPD for minimum assertion widthDuncan Laurie2019-01-081-0/+10
* soc/intel/cannonlake: Enable CNVi based on devicetreeMaulik V Vaghela2019-01-011-0/+4
* soc/intel/cannonlake: SATA and DMI power optimizeLijian Zhao2018-12-191-0/+4
* soc/intel/cannonlake: Add Acoustic featuresLijian Zhao2018-12-191-0/+11
* soc/intel/cannonlake: Add options for pcie ltrLijian Zhao2018-11-171-0/+2
* soc/intel/cannonlake: Remove depreciated UPD selectionLijian Zhao2018-11-051-5/+0
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-16 18:21:03 +0000