| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | soc/intel/cannonlake: Add FSP UPD for minimum assertion width | Duncan Laurie | 2019-01-08 | 1 | -0/+10 |
| * | soc/intel/cannonlake: Enable CNVi based on devicetree | Maulik V Vaghela | 2019-01-01 | 1 | -0/+4 |
| * | soc/intel/cannonlake: SATA and DMI power optimize | Lijian Zhao | 2018-12-19 | 1 | -0/+4 |
| * | soc/intel/cannonlake: Add Acoustic features | Lijian Zhao | 2018-12-19 | 1 | -0/+11 |
| * | soc/intel/cannonlake: Add options for pcie ltr | Lijian Zhao | 2018-11-17 | 1 | -0/+2 |
| * | soc/intel/cannonlake: Remove depreciated UPD selection | Lijian Zhao | 2018-11-05 | 1 | -5/+0 |
| * | soc/intel/cannonlake: Disable Legacy PME for Root ports | Subrata Banik | 2018-10-09 | 1 | -0/+3 |
| * | Move compiler.h to commonlib | Nico Huber | 2018-10-08 | 1 | -1/+0 |
| * | soc/intel/cannonlake: Move the FSP related callbacks to separate files | Rizwan Qureshi | 2018-10-04 | 1 | -0/+220 |
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index : coreboot.git | |
| Coreboot firmware sources | coreboot |
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