| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | treewide: Remove "this file is part of" lines | Patrick Georgi | 2020-05-11 | 1 | -1/+0 |
| * | treewide: replace GPLv2 long form headers with SPDX header | Patrick Georgi | 2020-05-06 | 1 | -12/+1 |
| * | treewide: Move "is part of the coreboot project" line in its own comment | Patrick Georgi | 2020-05-06 | 1 | -2/+1 |
| * | soc: Remove copyright notices | Patrick Georgi | 2020-03-18 | 1 | -1/+0 |
| * | soc/intel/cannonlake: Make use of gpio_pm_configure() | Subrata Banik | 2019-05-20 | 1 | -5/+14 |
| * | soc/intel: Add GPI interrupt config register offset info | Karthikeyan Ramasubramanian | 2019-04-29 | 1 | -0/+10 |
| * | soc/intel/cannonlake: Update GPIO definitions for Virtual GPIO | Rizwan Qureshi | 2019-02-26 | 1 | -10/+10 |
| * | soc/intel/cannonlake: Fix CNL-H GPIO pin map | Duncan Laurie | 2018-12-14 | 1 | -16/+36 |
| * | soc/intel/cannonlake: Add CNP PCH-H gpio pin definitions | praveen hodagatta pranesh | 2018-10-17 | 1 | -0/+170 |
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index : coreboot.git | |
| Coreboot firmware sources | coreboot |
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