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path: root/src/soc/intel/cannonlake/include
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* soc/intel/common/block: Move tco common functions into block/smbusSubrata Banik2019-01-101-9/+4
* soc/intel/cannonlake: Enable/Disable IPU based on devicetree switchV Sowmya2019-01-091-0/+4
* soc/intel/cannonlake: Add chipset event loggingDuncan Laurie2019-01-081-2/+0
* soc/intel/cannonlake: Add cannonlake ACPI GPIO opLijian Zhao2019-01-032-0/+2
* soc/intel/cannonlake: Amend comment typoLijian Zhao2018-12-191-1/+1
* soc/intel/cannonlake: Fix CNL-H GPIO pin mapDuncan Laurie2018-12-141-208/+304
* soc/intel/cannonlake: Delete unused macros in lpc.hSubrata Banik2018-11-271-10/+0
* src: Get rid of duplicated includesElyes HAOUAS2018-11-161-1/+0
* src: Remove unneeded include "{arch,cpu}/cpu.h"Elyes HAOUAS2018-11-122-2/+0
* src: Add missing include <stdint.h>Elyes HAOUAS2018-11-011-0/+2
* src: Add missing include <stdint.h>Elyes HAOUAS2018-10-301-0/+2
* soc/intel/cannonlake: Add back PM TIMER EMULATIONLijian Zhao2018-10-261-0/+3
* soc/intel/cannonlake: Add CNP PCH-H gpio pin definitionspraveen hodagatta pranesh2018-10-174-4/+660
* soc/intel/cannonlake: Add new cannon lake PCH-H supportpraveen hodagatta pranesh2018-10-171-1/+19
* src: Move common IA-32 MSRs to <cpu/x86/msr.h>Elyes HAOUAS2018-10-111-7/+0
* soc/intel/cannonlake: Make correct IRQ mapping for CNL SA and PCH PCI devicesSubrata Banik2018-10-091-4/+5
* soc/intel/cannonlake: Ensure FSP don't override ITSS IPCx registersSubrata Banik2018-10-091-0/+3
* Move compiler.h to commonlibNico Huber2018-10-082-2/+0
* src/soc/intel/cannonlake: Fix IA32_PLATFORM_DCA_CAP addressElyes HAOUAS2018-10-041-1/+1
* soc/intel/cannonlake: Correct ITSS port id.praveen hodagatta pranesh2018-09-211-1/+1
* soc/intel/cannonlake: Remove const for spd_smbus_addressLijian Zhao2018-09-201-1/+1
* soc/intel/cannonlake: Update PMC base address for CNP H and LPMaulik V Vaghela2018-08-301-0/+12
* soc/intel/cannonlake: Change LPDDR4 to MEMCFGLijian Zhao2018-08-281-15/+24
* cbtable: remove chromeos_acpi from cbtableJoel Kitching2018-08-221-1/+1
* soc/intel/common/block: Move common uart function to block/uartSubrata Banik2018-08-202-3/+4
* soc/intel/common/block: Move p2sb common functions into block/p2sbSubrata Banik2018-06-281-3/+0
* soc/intel/cannonlake: Remove DMA support for PTTSubrata Banik2018-06-221-4/+0
* soc/intel/common/block: Add common chip config blockSubrata Banik2018-06-061-0/+21
* src/soc: Get rid of whitespace before tabElyes HAOUAS2018-06-041-1/+1
* soc/intel/cannonlake: Add emmc/sdc port idLijian Zhao2018-02-221-0/+2
* soc/intel/cannonlake: Add provision to make CSME function disable in SMM modeSubrata Banik2018-02-221-0/+1
* src/soc: Fix various typosJonathan Neuschäfer2018-02-202-3/+3
* soc/intel/cannonlake: Add missing GPIO pin definitionsLijian Zhao2018-02-162-32/+133
* soc/intel/cannonlake: Add Pch iSCLK programmingLijian Zhao2018-02-111-0/+1
* src/soc/intel/cannonlake: Update C-state latency control limitsVaibhav Shankar2018-01-231-7/+7
* mainboard/intel/cannonlake_rvp: Add support for MAX98373 speaker ampN, Harshapriya2018-01-231-0/+1
* soc/intel/cannonlake: Add audio NHLT supportLijian Zhao2018-01-231-0/+43
* soc/intel/cannonlake: Remove redundent CNL CPUID macrosSubrata Banik2018-01-091-7/+1
* soc/intel/cannonlake: provide LPDDR4 memory initNick Vaccaro2018-01-071-0/+106
* soc/intel/cannonlake: Correct PMC/GPIO routing informationLijian Zhao2018-01-051-0/+10
* src/soc/intel/cannonlake: Add _PRW for CNViBora Guvendik2017-12-131-9/+13
* soc/intel/cannonlake: Add support for D0 steppingLijian Zhao2017-12-111-0/+1
* soc/intel/cannonlake: Add PCH ID support in bootblock/report_platform.cSubrata Banik2017-12-081-2/+0
* soc/intel/cannonlake: Fix DSX_CFG macro name for AC_PRESENTFurquan Shaikh2017-12-051-1/+1
* soc/intel/cannonlake: fix gpio pin numbersBora Guvendik2017-11-171-165/+169
* soc/intel/{cannonlake,skylake}: Add _soc_ prefix in spi soc routineSubrata Banik2017-11-111-22/+0
* sb and soc: Enforce correct offset of member "chromeos" in global_nvs_tJonathan Neuschäfer2017-11-041-0/+2
* soc/intel/cannonlake: Use common p2sb driverLijian Zhao2017-10-271-0/+3
* soc/intel/cannonlake: Add support for C state and P stateShaunak Saha2017-10-261-1/+1
* soc/intel/cannonlake: Fix HECI error on resetLijian Zhao2017-10-191-1/+1
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