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path: root/src/soc/intel/cannonlake/romstage/romstage.c
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* treewide: Remove "this file is part of" linesPatrick Georgi2020-05-111-1/+0
* soc/intel/cannonlake: Use SPDX for GPL-2.0-only filesAngel Pons2020-04-061-13/+2
* soc: Remove copyright noticesPatrick Georgi2020-03-181-1/+0
* soc/intel/cannonlake: Refactor pch_early_init() codeUsha P2019-12-261-0/+2
* soc/intel: Rename <intelblocks/chip.h>Kyösti Mälkki2019-09-291-1/+1
* soc/intel: Move fill_postcar_frame to memmap.cKyösti Mälkki2019-08-281-16/+0
* intel/car: Use common TS_START_ROMSTAGEKyösti Mälkki2019-08-261-2/+0
* soc/intel: Use common romstage codeKyösti Mälkki2019-08-261-14/+6
* arch/x86: Add <arch/romstage.h>Kyösti Mälkki2019-08-221-0/+1
* arch/x86: Adjust size of postcar stackKyösti Mälkki2019-07-041-1/+2
* soc/intel: Provide SPD manufacturer ID and module type to SMBIOSDuncan Laurie2019-06-211-1/+3
* src/soc/intel/common/smbios: Add addtional infos to dimm_infoChristian Walter2019-06-061-1/+5
* soc/intel: Fill DIMM serial number from SPDDuncan Laurie2019-05-181-0/+1
* soc/{amd,intel}/chip: Use local include for chip.hElyes HAOUAS2019-04-261-1/+2
* src: include <assert.h> when appropriateElyes HAOUAS2019-04-231-1/+0
* soc/intel/cannonlake: Allow mainboard to override DRAM part numberFurquan Shaikh2019-03-131-2/+17
* arch/io.h: Drop unnecessary includeKyösti Mälkki2019-03-041-1/+0
* soc/intel: Add mem_rank info in SMBIOSFrancois Toguo2019-02-181-0/+1
* soc/intel/cannonlake: Don't use CAR_GLOBALArthur Heymans2019-02-131-1/+0
* soc/intel/cannonlake: Fix chipset_power_state structureDuncan Laurie2019-01-081-3/+1
* Move compiler.h to commonlibNico Huber2018-10-081-1/+0
* soc/intel/cannonlake: Move the FSP related callbacks to separate filesRizwan Qureshi2018-10-041-55/+0
* soc/intel/cannonlake: Move SkipMpInit config to FSPMLijian Zhao2018-09-281-0/+4
* soc/{amd,intel}: Use postcar_frame_add_romcache()Nico Huber2018-06-041-2/+1
* soc/{amd,intel}: Use CACHE_ROM_(BASE|SIZE)Nico Huber2018-05-311-2/+2
* compiler.h: add __weak macroAaron Durbin2018-04-241-1/+2
* soc/intel/cannonlake: Set DISB after Dram initLijian Zhao2018-04-191-0/+1
* soc/intel/cannonlake: Add VT-d and VMX programmingLijian Zhao2018-04-051-0/+5
* intel/fsp: Update cannonlake fsp headerLijian Zhao2018-02-141-7/+0
* soc/intel/cannonlake: Save DIMM information for SMBIOS Table type 17Subrata Banik2018-02-081-0/+83
* soc/intel/cannonlake: enable pch link in bootblockCaveh Jalali2018-01-251-3/+0
* soc/intel/cannonlake: Program DMI PCR settingsLijian Zhao2018-01-161-0/+3
* soc/intel/cannonlake: Tell FSPM UART port numberLijian Zhao2017-12-201-0/+1
* soc/intel/cannonlake: Fix HECI error on resetLijian Zhao2017-10-191-0/+4
* soc/intel/cannonlake: Set platform Debug Probe TypeLijian Zhao2017-10-181-0/+2
* soc/intel/cannonlake: Disable CPU ratio overrideLijian Zhao2017-10-031-0/+2
* soc/intel/cannonlake: Set IGD stolen memory size to 64MBSubrata Banik2017-09-051-0/+2
* soc/intel/cannonlake: Define Max PCIE Root PortsPratik Prajapati2017-09-011-1/+1
* soc/intel/cannonlake: Add PrmrrSize and C6DRAM configSubrata Banik2017-08-301-0/+2
* soc/intel/cannonlake: Init UPD params based on configPratik Prajapati2017-08-251-0/+31
* soc/intel/cannonlake: Enable common PMC code for CNLLijian Zhao2017-08-211-3/+6
* soc/intel/cannonlake: Add postcar stage supportLijian Zhao2017-08-151-1/+22
* Update files with no newline at the endMartin Roth2017-07-241-1/+1
* Revert "soc/intel/cannonlake: Add postcar stage support"Martin Roth2017-07-211-25/+1
* soc/intel/cannonlake: Add postcar stage supportLijian Zhao2017-07-211-1/+25
* soc/intel/cannonlake: Add minimal changes to call FSP MemoryinitLijian Zhao2017-07-191-0/+50
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