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path: root/src/soc/intel/cannonlake
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* soc/intel/{apl,cnl,dnv,icl,skl} : Use common cpu/intel/car/romstage.c codeSubrata Banik2019-08-271-0/+1
* intel/car: Use common TS_START_ROMSTAGEKyösti Mälkki2019-08-261-2/+0
* lib/bootblock: Add simplified entry with basetimeKyösti Mälkki2019-08-261-1/+1
* soc/intel: Use common romstage codeKyösti Mälkki2019-08-261-14/+6
* soc/intel/cannonlake: Add config to disable display audio codecAamir Bohra2019-08-262-0/+2
* arch/x86: Add <arch/romstage.h>Kyösti Mälkki2019-08-221-0/+1
* soc/intel/cnl: Add provision to configure SD controller write protect pinAamir Bohra2019-08-202-0/+5
* soc/intel/cannonlake: Add 4E/4F to early io initChristian Walter2019-08-161-1/+1
* soc/intel/cannonlake: Add more PCI Ids for CoffeelakeChristian Walter2019-08-161-0/+8
* intel/smm: Define struct ied_header just onceKyösti Mälkki2019-08-151-5/+0
* soc/intel: Rename some SMM support functionsKyösti Mälkki2019-08-153-11/+2
* intel/ice,sky,cannon: Drop unused EMRR and UNCORE_EMRR codeKyösti Mälkki2019-08-152-35/+1
* soc/intel: Drop spurious includesKyösti Mälkki2019-08-151-1/+0
* mainboard/google: Fix indirect includesKyösti Mälkki2019-08-152-2/+1
* cpu/x86/smm: Define single smm_subregion()Kyösti Mälkki2019-08-151-47/+0
* cpu/x86: Separate save_state struct headersKyösti Mälkki2019-08-131-0/+1
* arch/x86: Flip option NO_CAR_GLOBAL_MIGRATIONKyösti Mälkki2019-08-111-1/+0
* arch/x86: Enable POSTCAR_CONSOLE by defaultKyösti Mälkki2019-08-111-1/+0
* cpu/x86/smm: Drop SMI handler address from structKyösti Mälkki2019-08-092-5/+2
* soc/intel: Drop pmc_soc_restore_power_failure()Nico Huber2019-08-091-5/+0
* soc/intel/{cnl,icl}: Use new power-failure-state APINico Huber2019-08-092-55/+11
* soc/intel: Fix SMRAM base MSRKyösti Mälkki2019-08-081-3/+2
* arch/x86: Handle smm_subregion() failureKyösti Mälkki2019-08-081-0/+2
* arch/x86: Change smm_subregion() prototypeKyösti Mälkki2019-08-083-27/+14
* lib/stage_cache: Refactor Kconfig optionsKyösti Mälkki2019-08-081-1/+0
* cpu/x86/smm: Promote smm_subregion()Kyösti Mälkki2019-08-071-1/+1
* intel/icelake,skylake,cannonlake: Drop unused parameterKyösti Mälkki2019-08-071-5/+2
* soc/intel/{cnl,icl}: Add support to get LPSS controllers list from SOCAamir Bohra2019-08-051-0/+8
* soc/intel/cnl/graphics: Hook up libgfxinitNico Huber2019-08-051-14/+22
* soc/intel/common/block/uart: Update the UART PCI device referenceAamir Bohra2019-08-041-4/+4
* soc/intel/cannonlake: Enable ACPI timer emulation if PM timer is disabledAamir Bohra2019-08-021-1/+7
* soc/intel/cannonlake: Disable ACPI PM timer to reduce S0ix power usageSubrata Banik2019-08-021-0/+3
* soc/intel/common/pch: Move thermal kconfig selection into common/pchSubrata Banik2019-08-021-1/+0
* soc/intel/cannonlake/bootblock: Clear the GPI IS & IE registersDavid Wu2019-08-011-0/+5
* soc/intel/cannonlake: Enable FSP to use coreboot stack for cometlakeAamir Bohra2019-07-311-0/+2
* soc/intel/cannonlake: Enable PCH Thermal Sensor configuration for S0ixSumeet Pawnikar2019-07-312-0/+12
* soc/intel/cnl: Only print ME status one timeTim Wawrzynczak2019-07-301-1/+0
* soc/intel/cannonlake: Allow coreboot to handle required chipset lockdownSubrata Banik2019-07-301-0/+34
* soc/intel/cannonlake: Add new PCI IDsFelix Singer2019-07-301-1/+10
* soc/intel/{broad,cannon,sky}: Fix possible out-of-bounds readsJacob Garber2019-07-301-2/+2
* soc/intel/cannonlake: Correct the data type of serial_io_devAamir Bohra2019-07-291-1/+1
* soc/intel: Guard remaining SA_DEV_ROOT definitionKyösti Mälkki2019-07-251-0/+2
* soc/intel/cannonlake: Split the "internal PME" wake-up into more detailPaul Fagerburg2019-07-251-1/+81
* soc/intel: Expand SA_DEV_ROOT for ramstageKyösti Mälkki2019-07-212-12/+10
* soc/intel: Fix chip_info for PCH_DEV_PMCKyösti Mälkki2019-07-212-11/+2
* soc/intel/common: Add SOC specific function to get XHCI USB infoKarthikeyan Ramasubramanian2019-07-193-13/+36
* soc/intel: Use config_of()Kyösti Mälkki2019-07-185-12/+5
* soc/intel: Use config_of_path(SA_DEVFN_ROOT)Kyösti Mälkki2019-07-186-40/+23
* soc/intel/cannonlake: Add device Ids for new CFL SKUs supportLean Sheng Tan2019-07-171-3/+11
* soc/intel: Fix regression with hidden PCI devicesKyösti Mälkki2019-07-171-2/+2
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