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path: root/src/soc/intel/cannonlake
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* soc: Remove copyright noticesPatrick Georgi2020-03-1889-146/+0
* soc/intel/cannonlake: Set correct serirq modeJeremy Soller2020-03-173-4/+10
* soc/intel/*/smihandler: Only compile in TCO SMI handler if neededPatrick Georgi2020-03-121-0/+2
* soc/intel: fix eist enablingMatt Delco2020-03-101-1/+2
* intel/soc: skl,apl,cnl,icl,tgl: add INTRUDER relevant registersMichael Niewöhner2020-03-071-0/+5
* intel/soc: skl,apl,cnl,icl,tgl,common: enable TCO SMIs if selectedMichael Niewöhner2020-03-071-1/+1
* soc/intel/cpu: Select NO_FIXED_XIP_ROM_SIZEArthur Heymans2020-03-041-1/+0
* src: capitalize 'PCIe'Elyes HAOUAS2020-03-041-1/+1
* soc/intel/{common, skl, cnl, apl}: Move print_me_fw_version() to CSE libSridhar Siricilla2020-03-021-79/+1
* soc/intel/cannonlake: Plumb TetonGlacierMode into dtEdward O'Callaghan2020-02-282-0/+6
* soc/intel/{cnl,icl}: Avoid static 8254 clock gating on S3 resumeSubrata Banik2020-02-261-1/+1
* soc/intel/common/block: Move cse common functions into block/cseSubrata Banik2020-02-251-39/+1
* soc/intel/common/block: Move smihandler common functions into common codeSubrata Banik2020-02-251-40/+3
* soc/intel/cannonlake: Add TDC config for CMLMarx Wang2020-02-252-0/+113
* soc/intel/cnl: Rename hfsts into me_hfstsSridhar Siricilla2020-02-241-16/+11
* src/intel: Define HFSTS3 registerSridhar Siricilla2020-02-171-0/+14
* soc/intel/{cnl,icl,skl,tgl}/bootblock: Update text for DMI PCR 2774Wim Vervoorn2020-02-171-2/+2
* soc/intel{cnl,icl,skl,tgl}/bootblock: Make sure DMI PCR 2770 is setWim Vervoorn2020-02-171-0/+5
* vboot: remove VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT optionJoel Kitching2020-02-171-1/+0
* soc/intel/{cnl,icl,skl,tgl,common}: Make changes to send_heci_reset_req_messa...Sridhar Siricilla2020-02-091-1/+1
* soc/intel/{common,skl,cnl,icl,apl,tgl}: Move HFSTS1 register definition to SoCSridhar Siricilla2020-02-091-0/+28
* soc/intel: Add get_pmbaseEugene Myers2020-02-042-0/+9
* soc/intel/cannonlake: Allow Audio DSP OSC qualification for low power idleAamir Bohra2020-02-043-1/+16
* soc/intel: Remove duplicate CPUID entrySubrata Banik2020-02-041-1/+1
* soc/intel/cannonlake/bootblock: Add CML-S 2/4-Core MCH IDsGaggery Tsai2020-01-181-0/+2
* soc/intel/cannonlake: Add chip config for SATA strengthJamie Chen2020-01-183-0/+59
* soc/intel/{cnl,icl,skl, tgl}: Move SOC_INTEL_COMMON_BLOCK_THERMAL into SoC sp...Subrata Banik2020-01-161-0/+1
* soc/intel/cannonlake: Fix ASL compilation remarksSubrata Banik2020-01-142-8/+4
* soc/intel/{apl,cnl,icl,skl,tgl}: Make above 4GB MMIO resource properSubrata Banik2020-01-102-2/+8
* sb/intel/common: Add smbus_set_slave_addr()Kyösti Mälkki2020-01-091-4/+0
* soc/intel/{cnl,icl,tgl}: Move northbridge.asl into common/block/acpiSubrata Banik2020-01-091-324/+0
* soc/intel/cannonlake: Add VR config for CMLJamie Chen2020-01-082-0/+144
* soc/intel/cannonlake: Add Comet Lake H SA 4+2 Device IDJamie Chen2020-01-081-0/+1
* soc/intel/{apl,cnl,icl,skl,tgl}: Clean up SA ASL codeSubrata Banik2020-01-071-205/+191
* soc/intel/cannonlake: Add VR config for CFL, CNL and WHLPatrick Rudolph2020-01-062-17/+266
* soc/intel/{icl,cnl,tgl}: Always add PM1_TMR block to FADTMeera Ravindranath2019-12-311-10/+8
* soc/intel/cannonlake: Move GPIO PM configuration to soc levelEric Lai2019-12-262-0/+58
* soc/intel/cannonlake: Clean up report_cpu_info() functionUsha P2019-12-261-24/+4
* soc/intel/cannonlake: Refactor pch_early_init() codeUsha P2019-12-267-13/+35
* {drivers,soc}/intel/fsp2_0: Move chipset specific logo handling to SoCWim Vervoorn2019-12-192-0/+8
* src/soc/intel: Remove unused <stdlib.h>Elyes HAOUAS2019-12-193-3/+0
* src: Use '#include <smp/node.h>' when appropriateElyes HAOUAS2019-12-191-0/+1
* soc/intel{cannonlake,icelake}/northbridge.asl: Correct flash rangeWim Vervoorn2019-12-171-1/+1
* src/soc/intel/cannonlake: Bump MAX_CPU from 8->12Edward O'Callaghan2019-12-161-0/+4
* 3rdparty/fsp: Update to current master againNico Huber2019-12-161-0/+1
* soc/intel/{cnl,icl,skl,tgl}: Remove unused gpe0_en_* from chip.hFurquan Shaikh2019-12-121-6/+0
* include/device/pci_ids: Add Coffeelake U IGD P630Christian Walter2019-12-101-0/+1
* 3rdparts/fsp: Update fsp submoduleJohanna Schander2019-12-091-1/+1
* soc/intel/cannonlake: Configure GPIO PM configuration in bootblockSubrata Banik2019-12-035-17/+53
* soc/intel/cannonlake: Add gfx.asl fileMathew King2019-12-022-0/+23
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