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path: root/src/soc/intel/cannonlake
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* soc/intel/cannonlake: Tell FSPM UART port numberLijian Zhao2017-12-201-0/+1
* soc/intel/common/fast_spi: implement spi_flash_ctrlr_protect_region()Aaron Durbin2017-12-161-1/+0
* soc/intel/cannonlake: Fix UART2 serial log broken issueSubrata Banik2017-12-141-10/+10
* src/soc/intel/cannonlake: Add _PRW for CNViBora Guvendik2017-12-133-9/+48
* soc/intel/cannonlake: Add support for D0 steppingLijian Zhao2017-12-111-0/+1
* soc/intel/cannonlake: Clean up UART codeAamir Bohra2017-12-093-68/+47
* soc/intel/cannonlake: Add PCH ID support in bootblock/report_platform.cSubrata Banik2017-12-082-7/+44
* soc/intel/cannonlake: Make use of Intel common Graphics blockSubrata Banik2017-12-072-39/+5
* soc/intel/cannonlake: Fix DSX_CFG macro name for AC_PRESENTFurquan Shaikh2017-12-052-2/+2
* soc/intel/cannonlake: Initialize PMC controllerSubrata Banik2017-12-023-89/+32
* soc/intel/cannonlake: Add PM methods to power gate SD card controllerVaibhav Shankar2017-11-231-0/+17
* soc/intel/cannonlake: Invoke pmc and hard reset only if CSE fails to resetJohn Zhao2017-11-231-1/+3
* soc/intel/cannonlake: Add ACPI workaround for EMMCLijian Zhao2017-11-201-0/+20
* soc/intel/cannonlake: fix gpio pin numbersBora Guvendik2017-11-171-165/+169
* soc/intel/cannonlake: Add cpu.asl fileShaunak Saha2017-11-171-0/+43
* soc/intel/cannonlake: Fix and clean up xhci ACPI codeVaibhav Shankar2017-11-151-142/+0
* soc/intel/cannonlake: Define default LPSS clockLijian Zhao2017-11-131-0/+4
* soc/intel/cannonlake: Make use of Intel SPI common blockSubrata Banik2017-11-113-56/+2
* soc/intel/{cannonlake,skylake}: Add _soc_ prefix in spi soc routineSubrata Banik2017-11-113-24/+34
* soc/intel/cannonlake: Remove structure variable initialization with 0Subrata Banik2017-11-101-3/+0
* soc/intel/cannonlake: Add DSP supportLijian Zhao2017-11-041-0/+1
* soc/intel/cannonlake: Install common i2cLijian Zhao2017-11-044-0/+92
* sb and soc: Enforce correct offset of member "chromeos" in global_nvs_tJonathan Neuschäfer2017-11-041-0/+2
* soc/intel/cannonlake: Use SCS common codeBora Guvendik2017-11-014-0/+44
* soc/intel/cannonlake: Use common p2sb driverLijian Zhao2017-10-272-0/+4
* soc/intel/cannonlake: Add support for C state and P stateShaunak Saha2017-10-263-1/+136
* soc/intel/cannonlake: remove duplicate power_state migrationPatrick Georgi2017-10-261-17/+0
* soc/intel/cannonlake: Increase stack size from 4KiB to 8KiBJohn Zhao2017-10-231-0/+4
* soc/intel/cannonlake: Change max root port to 16Lijian Zhao2017-10-221-1/+1
* security/vboot: Move vboot2 to security kconfig sectionPhilipp Deppenwiese2017-10-222-3/+3
* soc/intel/cannonlake: Add platform.aslLijian Zhao2017-10-201-24/+2
* soc/intel/cannonlake: Fix HECI error on resetLijian Zhao2017-10-194-8/+10
* soc/intel/cannonlake: Use EBDA structure to store soc reserve memory sizeSubrata Banik2017-10-192-3/+5
* soc/intel/cannonlake: Add IGD Support and pre-OS display codeAbhay Kumar2017-10-193-0/+81
* soc/intel/cannonlake: Set platform Debug Probe TypeLijian Zhao2017-10-182-0/+11
* soc/intel/cannonlake: Update PCIE CLKREQ programingLijian Zhao2017-10-184-4/+36
* soc/intel/cannonlake: Add finalize functionLijian Zhao2017-10-184-0/+263
* soc/intel/cannonlake: Calculate soc reserved memory sizeSubrata Banik2017-10-181-0/+15
* soc/intel/cannonlake: Use EBDA area to store cbmem_top addressSubrata Banik2017-10-185-49/+76
* soc/intel/cannonlake: Refactor memory layout calculationSubrata Banik2017-10-181-48/+119
* soc/intel/cannonlake: Create acpi_get_sleep_type() to get previous sleep stateSubrata Banik2017-10-181-2/+8
* soc/intel/common: Clean up PMC library GPE handling APIFurquan Shaikh2017-10-121-2/+2
* soc/intel/cannonlake: add length information for communitiesBora Guvendik2017-10-121-0/+6
* soc/intel/cannonlake: Add ACPI platform sleep capabilityVaibhav Shankar2017-10-121-0/+20
* soc/intel/cannonlake: Change default UART number to 2Lijian Zhao2017-10-111-1/+1
* soc/intel/*lake: Load vbt when it's neededPatrick Georgi2017-10-091-6/+1
* soc/intel/common: refactor locate_vbt and vbt_getPatrick Georgi2017-10-061-9/+1
* soc/intel/cannonlake: Enable MRC cacheLijian Zhao2017-10-061-0/+2
* soc/intel/cannonlake: reduce bootblock sizeAaron Durbin2017-10-061-0/+4
* soc/intel/cannonlake: Add all the SOC level DSDT tablesLijian Zhao2017-10-058-0/+635
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