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path: root/src/soc/intel/cannonlake
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* soc/intel: Use of common reset code blockSubrata Banik2020-11-022-17/+2
* soc/intel: Add a driver for CNVi WiFi/BT controllersFurquan Shaikh2020-11-021-0/+1
* soc/intel: deduplicate ACPI timer emulationMichael Niewöhner2020-10-281-25/+0
* mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable`Michael Niewöhner2020-10-261-2/+0
* soc/intel: drop unneeded ISST configuration codeMichael Niewöhner2020-10-261-28/+0
* src: Include <arch/io.h> when appropriateElyes HAOUAS2020-10-261-1/+0
* {cpu,soc}/intel: deduplicate cpu codeMichael Niewöhner2020-10-242-42/+0
* soc/intel: convert XTAL frequency constant to KconfigMichael Niewöhner2020-10-213-7/+10
* soc/intel/common: add Kconfig for PM Timer emulation supportMichael Niewöhner2020-10-211-0/+1
* soc/intel/cnl: lock AES-NI feature if selectedMichael Niewöhner2020-10-191-0/+2
* soc/intel/*: drop useless XTAL shutdown qualification codeMichael Niewöhner2020-10-191-10/+5
* Revert "soc/intel/cannonlake: Enable ACPI timer emulation if PM timer is disa...Michael Niewöhner2020-10-191-6/+0
* soc/intel/cannonlake: Fix memory corruptionsJohn Zhao2020-10-191-2/+2
* soc/intel: Configure PAVP at compile-timeBenjamin Doron2020-10-121-0/+2
* soc/intel/cannonlake: Align cosmetics with Ice LakeAngel Pons2020-10-124-50/+46
* soc/intel/common/block/acpi: Factor out common gfx.aslSubrata Banik2020-10-082-7/+1
* soc/intel: remove duplicate weak versions of mainboard_get_dram_part_num()Nick Vaccaro2020-10-051-6/+0
* soc: move mainboard_get_dram_part_num prototype to memory_info.hNick Vaccaro2020-10-051-2/+0
* mb, soc: change mainboard_get_dram_part_num() prototypeNick Vaccaro2020-10-052-9/+17
* soc/intel/common/block/acpi: Factor out common ish.aslSubrata Banik2020-10-052-10/+1
* soc/intel/common/block/acpi: Factor out common platform.aslSubrata Banik2020-10-051-20/+0
* soc/intel/{cnl,icl,skl}: Convert 'platform.asl' to ASL 2.0 syntaxSubrata Banik2020-10-051-1/+1
* soc/intel/common/block/acpi: Factor out common smbus.aslSubrata Banik2020-10-052-9/+1
* soc/intel/common/block/acpi: Factor out common pch_glan.aslSubrata Banik2020-10-052-16/+2
* soc/intel: Make use of PMC low power program from common blockSubrata Banik2020-10-033-9/+6
* soc/intel: Move pch_misc_init() to common codeSubrata Banik2020-10-031-12/+0
* soc/intel: Move soc_pch_pirq_init() to common codeSubrata Banik2020-10-032-70/+2
* soc/intel: Move pch_enable_ioapic() to common codeSubrata Banik2020-10-031-23/+1
* drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES configShelley Chen2020-10-021-1/+0
* soc/intel/common/block/lpc: add acpi nameJonathan Zhang2020-09-281-1/+0
* soc/intel/common/block/acpi: Factor out common gpio_op.aslSubrata Banik2020-09-273-129/+2
* soc/intel/cannonlake: Align gpio_op.asl with TGLSubrata Banik2020-09-274-25/+11
* arch/x86: Introduce `ARCH_ALL_STAGES_X86_32`Angel Pons2020-09-261-4/+1
* soc/intel: Use ASL 2.0 syntax for GPIO ASL helper functionSubrata Banik2020-09-251-16/+15
* soc/intel/cnl: drop lpit.asl in favor of common versionMichael Niewöhner2020-09-241-98/+0
* Revert "soc/intel: Refactor do_global_reset() function"Furquan Shaikh2020-09-221-0/+15
* src/soc/intel: Drop unneeded empty linesElyes HAOUAS2020-09-218-11/+0
* soc/intel: Refactor do_global_reset() functionSubrata Banik2020-09-211-15/+0
* soc/intel: rename get_prmrr_sizeMichael Niewöhner2020-09-211-1/+1
* soc/intel/cnl: Use the common code to set the PchPmPwrCycDurV Sowmya2020-09-211-120/+1
* soc/intel/common/block/cse: Refactor cse_request_global_reset() functionSubrata Banik2020-09-191-1/+1
* soc/intel/cannonlake: add missing special function padsMichael Niewöhner2020-09-175-30/+38
* soc/intel/cannonlake: rename "RSVD" GPIOs to their correct namesMichael Niewöhner2020-09-176-130/+130
* soc/intel/cannonlake: fix GPIO community numbering in ACPIMichael Niewöhner2020-09-171-2/+2
* soc/intel/{cnl,icl,jsl,tgl}: Clean up chip.hSubrata Banik2020-09-141-1/+0
* soc/intel/cnl: Add ACPI support for PMC core OS driverMichael Niewöhner2020-09-141-0/+3
* soc/intel/common/cpu: Update COS mask calculation for NEM enhanced modeAamir Bohra2020-09-141-1/+1
* soc/intel/cannonlake: Add PCIe ports on PCH-HPatrick Rudolph2020-09-093-4/+180
* soc/intel: skl,cnl,icl,jsl,tgl: disable usb over-current pin by defaultMichael Niewöhner2020-09-061-11/+10
* soc/intel/cnl: Enable HECI3 depending on devicetreeFelix Singer2020-09-042-2/+2
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