summaryrefslogtreecommitdiffstats
path: root/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S
Commit message (Expand)AuthorAgeFilesLines
* treewide: Remove "this file is part of" linesPatrick Georgi2020-05-111-1/+0
* treewide: replace GPLv2 long form headers with SPDX headerPatrick Georgi2020-05-061-12/+1
* treewide: Move "is part of the coreboot project" line in its own commentPatrick Georgi2020-05-061-2/+1
* src: Remove unused 'include <cpu/x86/cache.h>'Elyes HAOUAS2020-05-011-1/+0
* soc: Remove copyright noticesPatrick Georgi2020-03-181-1/+0
* arch/x86: Restrict use of _car_global[start|end]Kyösti Mälkki2019-09-111-3/+3
* arch/x86: Link walkcbfs.S instead of including itArthur Heymans2019-01-081-1/+5
* soc/intel: Consolidate FSP CAR setup and teardown codePraveen hodagatta pranesh2018-10-251-0/+117