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path: root/src/soc/intel/common/block/cpu/mp_init.c
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* soc/intel/common: Add lunarlake device IDsAppukuttan V K2024-01-261-0/+1
* intelblocks/cpu/mp_init: Add missing ADL-S SKUs to CPU match tableMichał Żygowski2023-07-121-0/+4
* treewide: Drop the suffixes from ADL and RPL CPUID macros and stringsMichał Żygowski2023-07-121-7/+7
* soc/intel/alderlake: Add support for Raptor Lake S CPUsMax Fritz2023-07-121-0/+4
* soc/intel/meteorlake: Add QS(C0) stepping CPU IDMusse Abdullahi2023-06-291-0/+1
* soc/intel/meteorlake: Add B0 stepping CPU IDMusse Abdullahi2023-04-151-0/+1
* soc/intel: Use common codeflow for MP initArthur Heymans2023-02-231-6/+2
* arch/x86/include/cpu: introduce CPU_TABLE_END CPU table terminatorFelix Held2023-02-091-1/+1
* arch/x86/cpu: introduce and use device_match_maskFelix Held2023-02-081-50/+50
* tree: Drop Intel Ice Lake supportFelix Singer2023-01-191-2/+0
* soc/intel/cnl: Add Cometlake-H/S Q0 (10+2) CPU IDJeremy Soller2022-09-161-1/+2
* soc/intel/common/cpu: Remove the address-of (`&`) operator usageSubrata Banik2022-08-161-2/+2
* treewide: Remove unused <cpu/x86/msr.h>Elyes Haouas2022-07-201-1/+0
* soc/intel: Add Raptor Lake device IDszhixingma2022-06-281-0/+1
* soc/intel/mp_init: Skip before_post_cpus_init if !USE_COREBOOT_MP_INITSubrata Banik2022-06-221-0/+10
* soc/intel/cmn/block/cpu: Perform PRMRR sync on all coresSubrata Banik2022-06-221-0/+8
* intel/mp_init: Call `intel_reload_microcode()` before post_cpus_init()Subrata Banik2022-06-221-2/+1
* soc/intel/cmn/mp_init: Reload microcode patch before post_cpus_init()Subrata Banik2022-06-091-0/+3
* soc/intel/cmn/mp_init: Create helper function to load microcodeSubrata Banik2022-06-071-4/+8
* soc/intel/cmn/block/cpu: Set BIOS_DONE on all CPUsSubrata Banik2022-06-071-0/+11
* soc/intel: Add Raptor Lake device IDsBora Guvendik2022-05-161-0/+1
* soc/intel/common: Use mp_run_on_all_cpus_synchronously for APs MTRR initKane Chen2022-05-161-1/+2
* soc/intel/alderlake: Add new CPU IDLean Sheng Tan2022-04-041-0/+1
* soc/intel/alderlake: Update CPU IDs with correct steppingsLean Sheng Tan2022-04-041-4/+4
* soc/intel/common/block/cpu: Enable ROM caching in ramstageSubrata Banik2022-03-171-0/+9
* soc/intel/common: Include Meteor Lake device IDsWonkyu Kim2022-03-091-0/+2
* soc/intel/common: Add missing space before }Paul Menzel2022-01-101-1/+1
* soc/intel/common: Include Alder Lake-N device IDsUsha P2021-11-291-0/+1
* cpu/x86/mp_init: use cb_err as status return type in remaining functionsFelix Held2021-10-221-1/+1
* soc/intel/alderlake: Add CPU ID 0x906a4Meera Ravindranath2021-09-301-0/+1
* soc/intel: Add TGL-H CPUIDJeremy Soller2021-08-241-0/+1
* soc/intel/common/cpu: Handle non-zero BSP APIC ID in init_cpusMAULIK V VAGHELA2021-08-091-2/+13
* soc/intel/{common,alderlake}: Use generic name "Alderlake Platform"Sridhar Siricilla2021-06-111-3/+3
* soc/intel/alderlake: Update CPU and IGD Device IDsMaulik V Vaghela2021-05-141-0/+1
* soc/intel/block/cpu/mp_init.c: Remove weak functionsArthur Heymans2021-03-181-11/+0
* soc/intel/*: Get rid of custom microcode cachingPatrick Rudolph2021-02-011-15/+4
* soc/intel/commmon: Include Alder Lake device IDsVarshit Pandya2021-01-221-0/+1
* soc/intel/common: Add Elkhart Lake B0 CPU IDTan, Lean Sheng2020-08-271-0/+1
* soc/intel/common/block/cpu: Refactor init_cpus functionSubrata Banik2020-08-061-7/+17
* soc/intel/common: Include Alder Lake device IDsSubrata Banik2020-08-051-1/+3
* soc/intel/tigerlake: Add CPU ID for TGL B0Jamie Ryu2020-06-061-0/+1
* treewide: Remove "this file is part of" linesPatrick Georgi2020-05-111-1/+0
* soc/intel/common: Use SPDX for GPL-2.0-only filesAngel Pons2020-04-061-13/+2
* soc: Remove copyright noticesPatrick Georgi2020-03-181-1/+0
* soc/intel/common: Update Jasper Lake Device IDsMeera Ravindranath2020-02-251-0/+1
* soc/intel: Remove duplicate CPUID entrySubrata Banik2020-02-041-1/+0
* soc/intel/common: Add Elkhartlake Device IDsTan, Lean Sheng2020-01-221-0/+1
* src/soc/intel: Add Cometlake-S and CMP-H skusGaggery Tsai2019-12-021-1/+3
* soc/intel/common: Include Tigerlake device IDsRavi Sarawadi2019-11-051-0/+1
* soc/intel: Rename <intelblocks/chip.h>Kyösti Mälkki2019-09-291-1/+1
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