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path: root/src/soc/intel/common/block/pcie/pcie.c
Commit message (Expand)AuthorAgeFilesLines
* treewide: Remove "this file is part of" linesPatrick Georgi2020-05-111-1/+0
* soc/intel/common: Use SPDX for GPL-2.0-only filesAngel Pons2020-04-061-13/+2
* soc: Remove copyright noticesPatrick Georgi2020-03-181-1/+0
* soc/intel/common: Update Jasper Lake Device IDsMeera Ravindranath2020-02-251-8/+8
* soc/intel/common: Add Elkhartlake Device IDsTan, Lean Sheng2020-01-221-0/+7
* soc/intel/common: Add PCI device IDs for CMP-HGaggery Tsai2019-12-131-0/+24
* soc/intel/common: Add Jasperlake Device IDsrkanabar2019-12-101-0/+8
* soc/intel/common: Include Tigerlake device IDsRavi Sarawadi2019-11-051-0/+16
* intel/pci: Utilise pci_def.h for PCI_BRIDGE_CONTROLKyösti Mälkki2019-10-011-1/+2
* soc/intel/skylake: Add Lewisburg family PCH supportMaxim Polyakov2019-09-061-0/+40
* device/pciexp_device: Convert LTR non-snoop/snoop value into common macroSubrata Banik2019-03-271-6/+2
* {northbridge, soc, southbridge}/intel: Make use of generic set_subsystem()Subrata Banik2019-03-211-10/+1
* Fix 'unsigned int' to bare use of 'unsigned'Subrata Banik2019-03-191-1/+1
* coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner2019-03-081-1/+1
* soc/intel/common: Include cometlake PCH IDsRonak Kanabar2019-02-261-0/+16
* soc/intel/common: Include Icelake device IDsAamir Bohra2018-11-071-0/+16
* soc/intel/cannonlake: Add new cannon lake PCH-H supportpraveen hodagatta pranesh2018-10-171-1/+25
* soc/intel/common/block: Don't use device_t in ramstageElyes HAOUAS2018-09-181-1/+1
* pci: Move inline PCI functions to pci_ops.hPatrick Rudolph2018-04-201-0/+1
* soc/intel/common/block: Add option to have subsystem_id in common pci driverSubrata Banik2017-12-131-0/+10
* soc/intel/common: Add Cannonlake pci ids for commonLijian Zhao2017-08-041-0/+16
* soc/intel/common: Add Intel PCIe common codeAamir Bohra2017-05-221-0/+149
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