coreboot.git - Coreboot firmware sources

	Commit message (Expand)	Author	Age	Files	Lines
*	soc/intel/*: Use SSDT to pass A4GB and A4GS	Arthur Heymans	2022-05-16	1	-0/+2
*	intelblocks/pcie: Correct mapping between LCAP port and coreboot index	MAULIK V VAGHELA	2022-02-25	1	-1/+1
*	soc/intel/elkhartlake: Add PSE TSN support	Lean Sheng Tan	2022-01-25	1	-1/+3
*	soc/intel: Replace open-coded buffer length calculation	Angel Pons	2021-04-21	1	-4/+2
*	soc/intel: Fix typo in comment	Angel Pons	2021-04-21	1	-1/+1
*	soc/intel: Rename and move MISCCFG_GPIO_PM_CONFIG_BITS definition to soc/gpio.h	Subrata Banik	2021-03-27	1	-1/+1
*	soc/intel/{adl,jsl,ehl,tgl}: Remove ITSS polarity restore	Aamir Bohra	2021-02-24	1	-7/+0
*	soc/amd,intel: Drop s3_resume parameter on FSP-S functions	Kyösti Mälkki	2021-02-09	1	-2/+1
*	soc/intel: hook up new gpio device in the soc chips	Michael Niewöhner	2020-12-30	1	-0/+3
*	soc/intel/elkhartlake: Update PCI device definition	Tan, Lean Sheng	2020-12-14	1	-12/+6
*	soc/intel/common/block/lpc: add acpi name	Jonathan Zhang	2020-09-28	1	-2/+0
*	soc/intel/elkhartlake: Do initial SoC commit till ramstage	Tan, Lean Sheng	2020-09-08	1	-0/+180