| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | soc/intel/jasperlake: CNVi: Enable fewer wakeups to reduce SoC power consumption | Jamie Chen | 2022-04-22 | 1 | -0/+5 |
| * | soc/intel/{icl,tgl,jsl,ehl}: add LPIT support | Michael Niewöhner | 2021-01-11 | 1 | -0/+2 |
| * | soc/intel/jasperlake: Enable USB2 PHY SUS PG for s0ix qualification | Krishna Prasad Bhat | 2021-01-08 | 1 | -0/+3 |
| * | soc/intel: Make use of PMC low power program from common block | Subrata Banik | 2020-10-03 | 1 | -0/+1 |
| * | soc/intel/jasperlake: Fix PMC_GPE_DW mapping | Meera Ravindranath | 2020-08-18 | 1 | -8/+9 |
| * | treewide: Remove "this file is part of" lines | Patrick Georgi | 2020-05-11 | 1 | -1/+0 |
| * | soc/intel/jasperlake: Use SPDX for GPL-2.0-only files | Angel Pons | 2020-04-06 | 1 | -13/+2 |
| * | soc/intel/jasperlake: Remove Tiger Lake SoC code from Jasper Lake | Aamir Bohra | 2020-03-28 | 1 | -31/+12 |
| * | soc/intel/jasperlake: Add Jasper Lake SoC support | Aamir Bohra | 2020-03-28 | 1 | -0/+168 |
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