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path: root/src/soc/intel/skylake/bootblock/pch.c
Commit message (Expand)AuthorAgeFilesLines
* soc/intel: clean up dmi driver codeWonkyu Kim2022-04-201-1/+0
* soc/intel/skylake: move heci_init() from bootblock to romstageMatt DeVillier2022-01-271-4/+0
* soc/intel/skylake: Move `gspi_early_bar_init()` callAngel Pons2021-03-011-0/+3
* soc/intel/*: drop incomplete and unneeded check for DMI SRLOCKMichael Niewöhner2021-01-311-16/+1
* soc/intel/{skl,cnl,xsp,icl,tgl,ehl,adl,jsl}: use common LPC mirroringMichael Niewöhner2021-01-251-15/+2
* soc/intel/common/dmi: Move DMI defines into DMI driver headerSrinidhi N Kaushik2020-12-091-2/+1
* soc/intel: Configure P2SB before other PCH controllersFurquan Shaikh2020-11-291-1/+6
* treewide: Remove "this file is part of" linesPatrick Georgi2020-05-111-1/+0
* soc/intel/skylake: Use SPDX for GPL-2.0-only filesAngel Pons2020-04-061-13/+2
* soc: Remove copyright noticesPatrick Georgi2020-03-181-2/+0
* soc/intel/skylake: Control fixed IO decode from devicetreeWim Vervoorn2020-03-181-3/+10
* soc/intel/{cnl,icl,skl,tgl}/bootblock: Update text for DMI PCR 2774Wim Vervoorn2020-02-171-3/+3
* soc/intel{cnl,icl,skl,tgl}/bootblock: Make sure DMI PCR 2770 is setWim Vervoorn2020-02-171-0/+6
* soc/intel/skylake: Rename pch_init() codeUsha P2019-12-261-1/+1
* soc/intel/skylake: Refactor pch_early_init() codeUsha P2019-11-221-12/+2
* soc/{amd,intel}/chip: Use local include for chip.hElyes HAOUAS2019-04-261-1/+2
* coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner2019-03-081-3/+3
* arch/io.h: Drop unnecessary includeKyösti Mälkki2019-03-041-1/+0
* device/pci: Fix PCI accessor headersKyösti Mälkki2019-03-011-0/+1
* soc/intel/common/block: Move tco common functions into block/smbusSubrata Banik2019-01-101-35/+3
* src: Fix typoElyes HAOUAS2018-08-101-2/+2
* soc/intel/common/block: Move p2sb common functions into block/p2sbSubrata Banik2018-06-281-21/+4
* src: Get rid of device_tElyes HAOUAS2018-06-141-1/+1
* soc/intel/skylake: Move PCR DMI programming into bootblockSubrata Banik2018-03-091-3/+30
* soc/intel/skylake: Make use of common CSE code for skylakeSubrata Banik2017-11-151-22/+3
* soc/intel/skylake: Add support in SKL for PMC common codeShaunak Saha2017-10-051-0/+1
* soc/intel/skylake: Enable common LPC IPRavi Sarawadi2017-10-031-72/+4
* soc/intel/skylake: Fix PMC address range setup for PCH-HNico Huber2017-07-111-2/+8
* soc/intel/skylake: Set generic I/O decode ranges earlyNico Huber2017-07-111-3/+3
* soc/intel/skylake: Use intel/common/block/smbus codeAamir Bohra2017-05-091-3/+4
* soc/intel/skylake: Clean up code by using common FAST_SPI moduleBarnali Sarkar2017-05-021-34/+2
* soc/intel/skylake: Use ITSS common codeBora Guvendik2017-04-281-12/+4
* soc/intel/skylake: Use RTC common codeSubrata Banik2017-04-101-10/+2
* soc/intel/skylake: Use common PCR moduleSubrata Banik2017-04-101-20/+33
* soc/pci_devs.h: Use consistent naming in soc/pci_devs.hSubrata Banik2017-03-281-1/+1
* soc/intel/skylake: Fix remaining issues detected by checkpatchLee Leahy2017-03-171-1/+1
* soc/intel/skylake: Wrap lines at 80 columnsLee Leahy2017-03-171-2/+2
* soc/skylake: Move IO decode range out from pch_lpc_initTeo Boon Tiong2016-11-301-11/+16
* skylake: Prepare GPE for use in bootblockDuncan Laurie2016-10-271-0/+3
* soc/intel/skylake: Enable HECI BAR for ME communicationSubrata Banik2016-10-161-0/+23
* soc/intel/skylake: Move bootblock specific code from skylake/romstageNaresh G Solanki2016-08-181-2/+203
* skylake: Do FspTempRamInit only for FSP1.1 & tidy up PCH early initRizwan Qureshi2016-08-181-0/+9
* soc/intel/skylake: Add C entry bootblock supportSubrata Banik2016-07-281-1/+17
* intel/skylake: unconditionally set SPI controller BARAaron Durbin2016-02-041-0/+22
* tree: drop last paragraph of GPL copyright headerPatrick Georgi2015-10-311-4/+0
* soc/intel: Add Skylake SOC supportLee Leahy2015-07-161-43/+4
* soc/intel/skylake: Use Broadwell as comparision base for Skylake SOCLee Leahy2015-07-161-0/+79
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