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path: root/src/soc/intel/skylake/bootblock
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* soc/intel/skylake: Clean up report_cpu_info() functionUsha P2019-11-271-20/+4
* soc/intel/skylake: Refactor pch_early_init() codeUsha P2019-11-222-14/+3
* soc/intel/skylake: drop support for FSP 1.1Michael Niewöhner2019-10-261-4/+0
* src/pci_ids: add missing Intel Kaby Lake iGPU PCIIDsMaxim Polyakov2019-10-041-6/+16
* src/pci_ids: add missing Intel Skylake iGPU PCIIDsMaxim Polyakov2019-10-041-2/+10
* pci_ids: rename PCI_DEVICE_ID_INTEL_SKL_ID_HMaxim Polyakov2019-09-301-1/+1
* soc/intel/skylake: Add Lewisburg family PCH supportMaxim Polyakov2019-09-061-0/+13
* soc/intel/skylake: Remove duplicated PCI IdMaxim Polyakov2019-08-301-2/+1
* lib/bootblock: Add simplified entry with basetimeKyösti Mälkki2019-08-261-1/+1
* soc/intel/skl: Add C232 chipset and reorder IDsFelix Singer2019-07-311-2/+3
* src/soc/intel/skylake/bootblock: Add SPT C236 to PCH TableChristian Walter2019-06-081-0/+1
* soc/intel: Add some missing MCH PCIe IDsKeno Fischer2019-06-071-0/+3
* soc/intel/skylake: Add PCI Id for Kabylake DTChristian Walter2019-05-231-0/+1
* soc/skylake: Add missing PCH IDsMarius Genheimer2019-05-061-0/+5
* soc/{amd,intel}/chip: Use local include for chip.hElyes HAOUAS2019-04-261-1/+2
* coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner2019-03-082-5/+5
* soc/intel/skylake: Add H110 PCH seriesMaxim Polyakov2019-03-061-0/+1
* soc/intel/skylake: Add new Northbridge and IGD IDsMaxim Polyakov2019-03-061-0/+2
* arch/io.h: Drop unnecessary includeKyösti Mälkki2019-03-042-2/+0
* device/pci: Fix PCI accessor headersKyösti Mälkki2019-03-012-0/+2
* soc/intel/common/block: Move tco common functions into block/smbusSubrata Banik2019-01-101-35/+3
* soc/intel: Clean mess around UART_DEBUGNico Huber2019-01-091-1/+1
* Remove intel/skylake/bootblock/timestamp.incKyösti Mälkki2018-12-241-33/+0
* cpuid: Add helper function for cpuid(1) functionsSubrata Banik2018-12-131-7/+8
* soc/intel/skylake: Add PCH sku id's supported for KBLPraveen hodagatta pranesh2018-11-081-0/+3
* src: Replace MSR addresses with macrosElyes HAOUAS2018-10-111-2/+2
* soc/intel/common/block: Move common uart function to block/uartSubrata Banik2018-08-201-1/+2
* src: Fix typoElyes HAOUAS2018-08-101-2/+2
* src/soc/intel: Add AML IGD in platform reportingGaggery Tsai2018-08-061-0/+1
* src/soc: Use "foo *bar" instead of "foo* bar"Elyes HAOUAS2018-07-091-1/+1
* soc/intel/common/block: Move p2sb common functions into block/p2sbSubrata Banik2018-06-281-21/+4
* src: Get rid of device_tElyes HAOUAS2018-06-142-6/+6
* bootblock: Allow more timestamps in bootblock_main_with_timestamp()Julius Werner2018-05-221-1/+1
* soc/intel: Add KBL-S MCH and some KBL PCH supportGaggery Tsai2018-03-261-0/+5
* soc/intel/skylake: Move PCR DMI programming into bootblockSubrata Banik2018-03-091-3/+30
* soc/intel/skylake: Add Kabylake PCH H device ID'sV Sowmya2018-02-071-0/+3
* soc/intel/skylake: Clean up the skylake PCH H device ID macrosV Sowmya2018-01-251-3/+3
* ic2/designware: Move Intel i2c logic to shared driverChris Ching2017-12-221-1/+1
* soc/intel/skylake: Clean up bootblock/report_platform.cSubrata Banik2017-12-081-6/+19
* soc/intel/skylake: Clean up UART codeAamir Bohra2017-12-071-57/+0
* soc/intel/skylake: Make use of common CSE code for skylakeSubrata Banik2017-11-151-22/+3
* soc/intel/skylake: Add support in SKL for PMC common codeShaunak Saha2017-10-051-0/+1
* soc/intel/skylake: Enable common LPC IPRavi Sarawadi2017-10-031-72/+4
* soc/intel/skylake: add Kabylake Celeron base SKUGaggery Tsai2017-09-221-0/+2
* soc/intel/skylake: Add proper support to enable UART2 in 16550 modeSubrata Banik2017-08-161-5/+10
* soc/intel/common/uart: Refactor uart_common_initFurquan Shaikh2017-08-101-5/+1
* soc/intel/skylake: Fix PMC address range setup for PCH-HNico Huber2017-07-111-2/+8
* soc/intel/skylake: Set generic I/O decode ranges earlyNico Huber2017-07-111-3/+3
* soc/intel/skylake: Remove unnecessary P-State and Flex Ratio assignmentBarnali Sarkar2017-07-012-74/+0
* soc/intel/skylake: Use CPU MP Init Common codeBarnali Sarkar2017-06-231-0/+1
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