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path: root/src/soc/intel/skylake/bootblock
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* soc/intel/skylake: Clean up bootblock/report_platform.cSubrata Banik2017-12-081-6/+19
* soc/intel/skylake: Clean up UART codeAamir Bohra2017-12-071-57/+0
* soc/intel/skylake: Make use of common CSE code for skylakeSubrata Banik2017-11-151-22/+3
* soc/intel/skylake: Add support in SKL for PMC common codeShaunak Saha2017-10-051-0/+1
* soc/intel/skylake: Enable common LPC IPRavi Sarawadi2017-10-031-72/+4
* soc/intel/skylake: add Kabylake Celeron base SKUGaggery Tsai2017-09-221-0/+2
* soc/intel/skylake: Add proper support to enable UART2 in 16550 modeSubrata Banik2017-08-161-5/+10
* soc/intel/common/uart: Refactor uart_common_initFurquan Shaikh2017-08-101-5/+1
* soc/intel/skylake: Fix PMC address range setup for PCH-HNico Huber2017-07-111-2/+8
* soc/intel/skylake: Set generic I/O decode ranges earlyNico Huber2017-07-111-3/+3
* soc/intel/skylake: Remove unnecessary P-State and Flex Ratio assignmentBarnali Sarkar2017-07-012-74/+0
* soc/intel/skylake: Use CPU MP Init Common codeBarnali Sarkar2017-06-231-0/+1
* soc/intel/skylake: Use CPU common library codeBarnali Sarkar2017-06-091-26/+7
* soc/intel/skylake: Move update microcode from cbfs to mp_ops callbacksBarnali Sarkar2017-06-091-2/+1
* soc/intel/skylake: Use PCI IDs from device/pci_ids.hSubrata Banik2017-06-061-38/+43
* soc/intel/skylake: Add config for cpu base clock frequencyAamir Bohra2017-06-051-1/+1
* soc/intel/common/block: add bios caching to fast spi moduleAaron Durbin2017-06-051-26/+1
* intel/common/block/i2c: Add common block for I2C and use the same in SoCsRizwan Qureshi2017-05-182-92/+2
* soc/intel/skylake: Use intel/common/block/smbus codeAamir Bohra2017-05-092-49/+4
* soc/intel/skylake: Clean up code by using common FAST_SPI moduleBarnali Sarkar2017-05-022-58/+9
* soc/intel/skylake: Use ITSS common codeBora Guvendik2017-04-281-12/+4
* soc/intel: Unify `timestamp.inc`Paul Menzel2017-04-251-4/+3
* lib: provide clearer devicetree semanticsAaron Durbin2017-04-251-2/+2
* soc/intel/skylake: Add ID's for Kabylake-RNaresh G Solanki2017-04-241-0/+3
* soc/intel/skylake: Use intel/common/uart driverAamir Bohra2017-04-111-24/+5
* soc/intel/skylake: Use LPSS common libraryAamir Bohra2017-04-112-19/+10
* soc/intel/skylake: Use RTC common codeSubrata Banik2017-04-101-10/+2
* soc/intel/skylake: Use common PCR moduleSubrata Banik2017-04-102-23/+43
* soc/intel/skylake: Add support for GSPI controllerFurquan Shaikh2017-04-061-0/+2
* soc/intel/skylake: Clean up code by using common System Agent moduleSubrata Banik2017-03-281-43/+0
* soc/pci_devs.h: Use consistent naming in soc/pci_devs.hSubrata Banik2017-03-281-1/+1
* soc/intel/common/block: Add cache as ram init and teardown codeSubrata Banik2017-03-281-283/+0
* soc/intel/skylake: Use C entry code for MTRR programmingSubrata Banik2017-03-242-41/+30
* soc/intel/skylake: Fix remaining issues detected by checkpatchLee Leahy2017-03-173-3/+3
* soc/intel/skylake: Wrap lines at 80 columnsLee Leahy2017-03-172-4/+4
* soc/intel/skylake: Add int to unsignedLee Leahy2017-03-171-2/+2
* soc/intel/skylake: Clean up CPU codeSubrata Banik2017-03-061-1/+1
* soc/intel/skylake: Add CPU, PCH, MCH, IGD, XHCI and UART IDs for SKL/KBL HALO...Sooi, Li Cheng2017-02-161-0/+13
* PCI ops: MMCONF_SUPPORT_DEFAULT is requiredKyösti Mälkki2016-12-071-2/+2
* soc/skylake: Move IO decode range out from pch_lpc_initTeo Boon Tiong2016-11-302-11/+17
* soc/intel/skylake: Initialize UART based on CONFIG_UART_DEBUGTeo Boon Tiong2016-11-281-1/+1
* soc/intel/common/lpss_i2c: simplify API and use common config structureAaron Durbin2016-11-111-13/+1
* soc/intel/skylake: Add device id for PCH-YNaresh G Solanki2016-11-071-6/+7
* skylake: Prepare GPE for use in bootblockDuncan Laurie2016-10-271-0/+3
* soc/intel/skylake: Enable HECI BAR for ME communicationSubrata Banik2016-10-161-0/+23
* Fix newlines at the end of filesMartin Roth2016-09-021-1/+0
* soc/intel/skylake: Include Kabylake specific IGD Device IDsBarnali Sarkar2016-08-301-0/+3
* soc/intel/skylake: Correct Cache as ram sizeRizwan Qureshi2016-08-181-2/+2
* soc/intel/skylake: Move bootblock specific code from skylake/romstageNaresh G Solanki2016-08-186-3/+607
* skylake: Do FspTempRamInit only for FSP1.1 & tidy up PCH early initRizwan Qureshi2016-08-182-5/+15
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