coreboot.git - Coreboot firmware sources

	Commit message (Expand)	Author	Age	Files	Lines
...
*	Remove extra newlines from the end of all coreboot files.	Martin Roth	2016-07-31	1	-1/+0
*	intel/fsp1_1: Add C entry support to locate FSP Temp RAM Init	Subrata Banik	2016-07-28	1	-5/+8
*	soc/intel/skylake: Add C entry bootblock support	Subrata Banik	2016-07-28	5	-65/+121
*	soc/intel/skylake: Do cache as ram and prepare for C entry	Subrata Banik	2016-07-28	2	-0/+342
*	soc/intel: Update license headers	Martin Roth	2016-04-14	1	-0/+14
*	intel/skylake: unconditionally set SPI controller BAR	Aaron Durbin	2016-02-04	2	-17/+23
*	intel/skylake: Remove check for Microcode loaded by ME	Martin Roth	2016-01-12	1	-22/+1
*	tree: drop last paragraph of GPL copyright header	Patrick Georgi	2015-10-31	3	-12/+0
*	cpu/mtrr.h: Fix macro names for MTRR registers	Alexandru Gagniuc	2015-10-15	1	-7/+7
*	skylake: Leave SPI controller enabled	Lee Leahy	2015-10-11	1	-5/+0
*	skylake: SPI code cleanup	Lee Leahy	2015-10-11	1	-4/+6
*	x86: bootblock: remove linking and program flow from build system	Aaron Durbin	2015-09-09	1	-1/+0
*	skylake: fix garbled patch from upstream	Aaron Durbin	2015-08-13	1	-13/+12
*	Skylake: Fix microcode reload in bootblock cpu init	Rizwan Qureshi	2015-07-29	1	-1/+23
*	soc/intel: Add Skylake SOC support	Lee Leahy	2015-07-16	5	-73/+83
*	soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC	Lee Leahy	2015-07-16	5	-0/+285