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path: root/src/soc/intel/skylake/cpu.c
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* soc/intel/common/sgx: Define and use soc_fill_sgx_param()Pratik Prajapati2017-09-151-0/+15
* cpu/x86/mp_init: remove adjust_cpu_apic_entry()Aaron Durbin2017-09-111-11/+0
* soc/intel/skylake: Use common mca_configure() APIPratik Prajapati2017-09-021-24/+4
* soc/intel/skylake: Fix SGX init sequencePratik Prajapati2017-08-211-10/+4
* intel/common/mp_init: Refactor MP Init code to get rid of microcode paramPratik Prajapati2017-08-211-2/+2
* intel/common/sgx: Use intel_mp_current_microcode() to get microcode pointerPratik Prajapati2017-08-211-2/+2
* soc/intel/skylake: Set PsysPL2 MSRShelley Chen2017-07-141-1/+16
* sgx: Move SGX code to intel/common/blockPratik Prajapati2017-07-101-2/+14
* soc/intel/skylake: Remove post SMM Relocation uCode loadingBarnali Sarkar2017-06-231-20/+1
* soc/intel/skylake: Use CPU MP Init Common codeBarnali Sarkar2017-06-231-85/+20
* soc/intel/skylake: Enable ACPI PM timer emulation on all CPUsSubrata Banik2017-06-091-3/+26
* soc/intel/skylake: Use CPU common library codeBarnali Sarkar2017-06-091-38/+5
* soc/intel/skylake: Move update microcode from cbfs to mp_ops callbacksBarnali Sarkar2017-06-091-0/+1
* soc/intel/skylake: Cache the MMIO BIOS regionAaron Durbin2017-06-091-0/+7
* src: change coreboot to lowercaseMartin Roth2017-06-071-1/+1
* soc/intel/skylake: Add config for cpu base clock frequencyAamir Bohra2017-06-051-1/+1
* soc/intel/skylake: Add option to enable/disable EISTSubrata Banik2017-05-161-1/+6
* soc/intel/skylake: Configure C-state interrupt response timeSubrata Banik2017-05-161-0/+41
* soc/intel/skylake: Enable MTRR checkFurquan Shaikh2017-05-081-0/+1
* soc/intel/skylake: Add ID's for Kabylake-RNaresh G Solanki2017-04-241-0/+1
* soc/intel/skylake: Add SGX initializationRobbie Zhang2017-03-231-14/+38
* soc/intel/skylake: Fix remaining issues detected by checkpatchLee Leahy2017-03-171-2/+1
* soc/intel/skylake: Wrap lines at 80 columnsLee Leahy2017-03-171-1/+2
* soc/intel/skylake: Add int to unsignedLee Leahy2017-03-171-2/+2
* soc/intel/skylake: Clean up CPU codeSubrata Banik2017-03-061-1/+1
* soc/intel/skylake: Fix broken suspend-resumeFurquan Shaikh2017-02-221-1/+1
* intel/skylake: add function is_secondary_thread()Robbie Zhang2017-02-171-0/+11
* soc/intel/skylake: Add CPU, PCH, MCH, IGD, XHCI and UART IDs for SKL/KBL HALO...Sooi, Li Cheng2017-02-161-0/+4
* soc/intel/skylake: Perform CPU MP Init before FSP-S InitSubrata Banik2017-02-141-10/+25
* soc/intel/skylake: set TCC activation by BSP onlySumeet Pawnikar2016-12-261-4/+4
* skylake: Update the thermal time window for throttling actionSumeet Pawnikar2016-11-141-0/+4
* soc/intel/skylake: Add Kabylake device IdsRizwan Qureshi2016-08-061-0/+2
* src/soc: Capitalize CPU, ACPI, RAM and ROMElyes HAOUAS2016-07-311-2/+2
* soc/intel/skylake: convert to using common MP and SMM initAaron Durbin2016-05-061-82/+65
* cpu/x86/mp_init: remove unused callback argumentsAaron Durbin2016-05-021-6/+6
* intel/skylake: Enable PROCHOTPratik Prajapati2016-03-291-0/+6
* x86 chipsets: utilize x86_setup_mtrrs_with_detect()Aaron Durbin2016-03-081-2/+1
* Skylake: Support Intel Speed Shift Technology based on configSubrata Banik2016-03-011-0/+29
* intel/skylake: Thermal Design Power PL1 and PL2 Config Changespchandri2016-01-221-5/+9
* skylake: Set Pkg Power clamping bit in Power Limit MSRRizwan Qureshi2015-11-051-0/+5
* tree: drop last paragraph of GPL copyright headerPatrick Georgi2015-10-311-4/+0
* cpu/mtrr.h: Fix macro names for MTRR registersAlexandru Gagniuc2015-10-151-1/+1
* Skylake: remove the out-dated VR config and un-needed 24mhz calibrationrobbie zhang2015-10-111-115/+0
* skylake: only generate ACPI cpu entries onceAaron Durbin2015-08-271-2/+0
* skylake: Update microcode reload in ramstage.Rizwan Qureshi2015-07-291-0/+13
* soc/intel: Add Skylake SOC supportLee Leahy2015-07-161-216/+57
* soc/intel/skylake: Use Broadwell as comparision base for Skylake SOCLee Leahy2015-07-161-0/+735
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