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path: root/src/soc/intel/skylake/pmc.c
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* treewide: Remove "this file is part of" linesPatrick Georgi2020-05-111-1/+0
* soc/intel/skylake: Use SPDX for GPL-2.0-only filesAngel Pons2020-04-061-13/+2
* soc: Remove copyright noticesPatrick Georgi2020-03-181-3/+0
* soc/intel: Replace config_of_path() with config_of_soc()Kyösti Mälkki2019-10-021-1/+1
* soc/intel: Drop pmc_soc_restore_power_failure()Nico Huber2019-08-091-5/+0
* soc/intel/skylake: Use new power-failure-state APINico Huber2019-08-091-68/+28
* soc/intel: Use config_of_path(SA_DEVFN_ROOT)Kyösti Mälkki2019-07-181-7/+2
* soc/{amd,intel}/chip: Use local include for chip.hElyes HAOUAS2019-04-261-1/+2
* device/mmio.h: Add include file for MMIO opsKyösti Mälkki2019-03-041-0/+1
* soc/intel: Drop pmc_get_mainboard_power_failure_state_choice()Nico Huber2019-01-061-4/+2
* soc/intel/skylake: Set PCIEXPWAK_DIS if WAKE# pin is not enabledFurquan Shaikh2018-10-101-0/+25
* src: Get rid of device_tElyes HAOUAS2018-06-141-1/+5
* pci: Move inline PCI functions to pci_ops.hPatrick Rudolph2018-04-201-0/+1
* soc/intel/skylake: Move Enable power button SMI code from smi.c to pmc.cSubrata Banik2017-12-211-0/+16
* soc/intel/skylake: Implement pmc_soc_restore_power_failure as per EDSSubrata Banik2017-12-211-18/+44
* soc/intel/common/block: Add Intel common PMC controller support for KBL, APLSubrata Banik2017-12-021-101/+39
* soc/intel/skylake: Add support in SKL for PMC common codeShaunak Saha2017-10-051-1/+2
* soc/intel/skylake: refactor rtc failure checkingAaron Durbin2017-09-201-13/+1
* vboot: remove init_vbnv_cmos()Aaron Durbin2017-09-201-6/+1
* soc/intel/skylake: Split AC/DC settings for Deep Sx configDuncan Laurie2017-04-131-7/+10
* soc/intel/skylake: Use common PCR moduleSubrata Banik2017-04-101-1/+2
* soc/intel/skylake: Add CPU, PCH, MCH, IGD, XHCI and UART IDs for SKL/KBL HALO...Sooi, Li Cheng2017-02-161-0/+1
* skylake: Prepare GPE for use in bootblockDuncan Laurie2016-10-271-38/+1
* soc/intel/skylake: Use init_vbnv_cmos from vboot vbnvFurquan Shaikh2016-07-281-23/+4
* vboot: Separate vboot from chromeosFurquan Shaikh2016-07-281-7/+5
* soc/intel/skylake: use common Intel ACPI hardware definitionsAaron Durbin2016-07-151-1/+1
* chromeos: Remove CONFIG_VBNV_SIZE variableDuncan Laurie2016-02-091-1/+2
* intel/skylake: ensure the RTC time is setAaron Durbin2015-11-131-0/+3
* Skylake:Set DISB inside romstage after mrc initDhaval Sharma2015-09-081-2/+0
* skylake: remove ec_smi_gpio and alt_gp_smi_enAaron Durbin2015-08-141-3/+0
* skylake: provide GPE0 routing devicetree configurationAaron Durbin2015-08-141-3/+40
* skylake: clear write-1-to-clear fields in power regsAaron Durbin2015-08-141-13/+18
* skylake: set DISB in GEN_PMCON_A register properlyAaron Durbin2015-08-141-1/+1
* skylake: fill out gen_pmcon_* bitfieldsAaron Durbin2015-08-141-4/+9
* skylake: Add Deep Sx configuration for wake pinsDuncan Laurie2015-08-131-0/+12
* soc/intel: Add Skylake SOC supportLee Leahy2015-07-161-0/+254
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