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path: root/src/soc/intel/skylake/romstage/romstage.c
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* soc/intel/skylake: Extract fsp_params.c out of romstage.cAngel Pons2021-03-011-187/+2
* soc/intel: Drop `romstage_pch_init()` functionAngel Pons2021-03-011-2/+3
* src: Remove unused <cpu/x86/smm.h>Elyes HAOUAS2021-02-011-1/+0
* soc/intel/skylake: Drop always-zero ProbelessTrace dt settingAngel Pons2020-12-141-1/+1
* soc/intel/skylake: Drop never-set DdrFreqLimit dt settingAngel Pons2020-12-141-1/+1
* soc/intel/skl: set PEG port state to autoMichael Niewöhner2020-12-071-0/+3
* soc/intel: rename get_prmrr_sizeMichael Niewöhner2020-09-211-1/+1
* soc/intel/skylake: Refactor PEG configurationFelix Singer2020-08-141-12/+6
* soc/intel/skylake: Factor out unnecessary if-else-blockFelix Singer2020-08-141-19/+14
* soc/intel/skylake: Use PEG definitions from pci_devs.hFelix Singer2020-08-141-3/+3
* soc/intel/skylake: Refactor ternary expressionsFelix Singer2020-08-131-2/+2
* soc/intel/skylake: Enable TraceHub depending on devicetree configurationFelix Singer2020-07-291-1/+3
* soc/intel/skylake: Enable SMBus depending on devicetree configurationFelix Singer2020-07-291-2/+4
* Revert "src: Remove unused include <cpu/x86/smm.h>"Patrick Rudolph2020-07-281-0/+1
* src: Remove unused include <cpu/x86/smm.h>Elyes HAOUAS2020-07-261-1/+0
* soc/intel/skl: Drop weak mainboard_memory_init_paramsAngel Pons2020-05-121-5/+0
* treewide: Remove "this file is part of" linesPatrick Georgi2020-05-111-1/+0
* soc/intel/skylake: Use SPDX for GPL-2.0-only filesAngel Pons2020-04-061-13/+2
* soc: Remove copyright noticesPatrick Georgi2020-03-181-1/+0
* soc/intel/skylake: Rename pch_init() codeUsha P2019-12-261-1/+1
* soc/skylake: Write the P2SB IBDF and HBDF registers in corebootAngel Pons2019-11-271-6/+3
* soc/intel/skylake: Refactor pch_early_init() codeUsha P2019-11-221-1/+2
* soc/intel/sgx: convert SGX and PRMRR devicetree options to KconfigMichael Niewöhner2019-11-041-1/+2
* soc/intel/skylake: move/rename files after drop of FSP 1.1Michael Niewöhner2019-10-261-0/+344
* soc/intel/skylake: drop support for FSP 1.1Michael Niewöhner2019-10-261-261/+0
* soc/intel: Replace config_of_path() with config_of_soc()Kyösti Mälkki2019-10-021-2/+2
* src/{northbridge,soc}: Remove not used #include <elog.h>Elyes HAOUAS2019-09-121-1/+0
* soc/intel: Use config_of()Kyösti Mälkki2019-07-181-7/+7
* soc/intel: Replace uses of dev_find_slot()Kyösti Mälkki2019-07-041-1/+1
* Clean up unused arch/early_variables.h headerArthur Heymans2019-05-291-1/+0
* intel/fsp1_1: Drop remnants of `pei_data`Nico Huber2019-05-071-4/+0
* intel/fsp1_1: Move MRC cache pointers into `romstage_params`Nico Huber2019-05-071-0/+6
* soc/{amd,intel}/chip: Use local include for chip.hElyes HAOUAS2019-04-261-1/+2
* src: Use include <reset.h> when appropriateElyes HAOUAS2019-03-291-1/+0
* src: Drop unused 'include <romstage_handoff.h>'Elyes HAOUAS2019-03-181-1/+0
* coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner2019-03-081-1/+1
* src: Drop unused include <timestamp.h>Elyes HAOUAS2019-03-071-1/+0
* arch/io.h: Drop unnecessary includeKyösti Mälkki2019-03-041-1/+0
* arch/x86: Drop spurious arch/stages.h includesKyösti Mälkki2018-12-281-1/+0
* soc/intel/skylake: Drop FSP_CAR optionsNico Huber2018-11-231-4/+2
* src: Remove unneeded include <cbmem.h>Elyes HAOUAS2018-11-161-1/+0
* src: Remove unneeded include "{arch,cpu}/cpu.h"Elyes HAOUAS2018-11-121-1/+0
* soc/intel/skylake: Add support in SKL for PMC common codeShaunak Saha2017-10-051-0/+11
* vboot: Remove get_sw_write_protect_state callbackJulius Werner2017-07-181-8/+0
* soc/intel/skylake: Clean up code by using common FAST_SPI moduleBarnali Sarkar2017-05-021-4/+4
* intel MMA: Enable MMA with FSP2.0Pratik Prajapati2016-12-131-0/+19
* soc/intel/skylake: Add FSP 2.0 support in romstageBarnali Sarkar2016-09-151-7/+1
* soc/intel/skylake: Correct Cache as ram sizeRizwan Qureshi2016-08-181-1/+1
* soc/intel/skylake: restore MCHBAR and DMIBAR programmingRizwan Qureshi2016-08-171-0/+3
* soc/intel/skylake: Add C entry bootblock supportSubrata Banik2016-07-281-18/+0
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