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path: root/src/soc/intel/skylake/romstage
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* soc/intel: Rename heci_init to cse_initSubrata Banik2022-06-041-1/+1
* soc/intel/skylake: Hook up FSP hyper-threading setting to option APIFelix Singer2022-05-171-1/+2
* soc/intel/skylake: move heci_init() from bootblock to romstageMatt DeVillier2022-01-271-0/+3
* src/soc/intel: Remove unused <console/console.h>Elyes HAOUAS2022-01-101-1/+0
* skylake: Default to `BOARD_TYPE_DESKTOP` for PCH-HAngel Pons2021-09-031-1/+4
* soc/intel/skylake: Rename `Rmt` devicetree settingAngel Pons2021-07-141-1/+1
* soc/intel/skylake: Use `is_devfn_enabled()`Angel Pons2021-06-252-19/+7
* intel: mma: Use new CBFS APIJulius Werner2021-04-141-8/+4
* soc/intel/skylake: Drop unnecessary `ignore_vtd` optionAngel Pons2021-04-081-5/+0
* soc/intel: Hook up `SOC_INTEL_DISABLE_IGD` to `InternalGfx` UPDAngel Pons2021-04-081-1/+1
* soc/intel/skylake: Extract fsp_params.c out of romstage.cAngel Pons2021-03-013-187/+192
* soc/intel: Drop `romstage_pch_init()` functionAngel Pons2021-03-013-13/+3
* soc/intel/{skl,icl}: Move tco_configure() to bootblockAngel Pons2021-03-011-4/+0
* src: Remove unused <cpu/x86/smm.h>Elyes HAOUAS2021-02-011-1/+0
* soc/intel/skylake: Drop always-zero ProbelessTrace dt settingAngel Pons2020-12-141-1/+1
* soc/intel/skylake: Drop never-set DdrFreqLimit dt settingAngel Pons2020-12-141-1/+1
* soc/intel/skl: set PEG port state to autoMichael Niewöhner2020-12-071-0/+3
* soc/intel: rename get_prmrr_sizeMichael Niewöhner2020-09-211-1/+1
* soc/intel/skylake: Refactor PEG configurationFelix Singer2020-08-141-12/+6
* soc/intel/skylake: Factor out unnecessary if-else-blockFelix Singer2020-08-141-19/+14
* soc/intel/skylake: Use PEG definitions from pci_devs.hFelix Singer2020-08-141-3/+3
* soc/intel/skylake: Refactor ternary expressionsFelix Singer2020-08-131-2/+2
* soc/intel/skylake: Enable TraceHub depending on devicetree configurationFelix Singer2020-07-291-1/+3
* soc/intel/skylake: Enable SMBus depending on devicetree configurationFelix Singer2020-07-291-2/+4
* Revert "src: Remove unused include <cpu/x86/smm.h>"Patrick Rudolph2020-07-281-0/+1
* src: Remove unused include <cpu/x86/smm.h>Elyes HAOUAS2020-07-261-1/+0
* soc/intel/skl: Drop weak mainboard_memory_init_paramsAngel Pons2020-05-121-5/+0
* treewide: Remove "this file is part of" linesPatrick Georgi2020-05-113-3/+0
* soc/intel/skylake: Use SPDX for GPL-2.0-only filesAngel Pons2020-04-063-39/+6
* soc: Remove copyright noticesPatrick Georgi2020-03-183-5/+0
* soc/intel/skylake: Rename pch_init() codeUsha P2019-12-262-4/+4
* soc/skylake: Write the P2SB IBDF and HBDF registers in corebootAngel Pons2019-11-272-6/+8
* soc/intel/skylake: Refactor pch_early_init() codeUsha P2019-11-223-1/+30
* soc/intel/sgx: convert SGX and PRMRR devicetree options to KconfigMichael Niewöhner2019-11-041-1/+2
* soc/intel/skylake: move/rename files after drop of FSP 1.1Michael Niewöhner2019-10-262-1/+1
* soc/intel/skylake: drop support for FSP 1.1Michael Niewöhner2019-10-262-263/+1
* soc/intel: Replace config_of_path() with config_of_soc()Kyösti Mälkki2019-10-023-4/+4
* src/{northbridge,soc}: Remove not used #include <elog.h>Elyes HAOUAS2019-09-121-1/+0
* soc/intel/skylake: Add option to toggle Hyper-ThreadingPatrick Rudolph2019-09-101-0/+1
* soc/skylake: do not rely on P2SB data to generate DRHDAngel Pons2019-09-031-3/+4
* soc/intel: Move fill_postcar_frame to memmap.cKyösti Mälkki2019-08-281-29/+0
* soc/intel/{apl,cnl,dnv,icl,skl} : Use common cpu/intel/car/romstage.c codeSubrata Banik2019-08-271-1/+1
* intel/car: Use common TS_START_ROMSTAGEKyösti Mälkki2019-08-261-2/+0
* soc/intel: Use common romstage codeKyösti Mälkki2019-08-261-29/+18
* arch/x86: Add <arch/romstage.h>Kyösti Mälkki2019-08-221-0/+1
* arch/x86: Change smm_subregion() prototypeKyösti Mälkki2019-08-081-4/+2
* cpu/x86/smm: Promote smm_subregion()Kyösti Mälkki2019-08-071-1/+1
* soc/intel: Expand SA_DEV_ROOT for ramstageKyösti Mälkki2019-07-211-3/+3
* soc/intel: Use config_of()Kyösti Mälkki2019-07-182-10/+8
* soc/intel: Use config_of_path(SA_DEVFN_ROOT)Kyösti Mälkki2019-07-181-4/+2
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