| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | soc/intel/skylake: Clean up UART code | Aamir Bohra | 2017-12-07 | 1 | -2/+48 |
| * | soc/intel/skylake: Add support for all UART port index | Subrata Banik | 2017-08-21 | 1 | -2/+2 |
| * | soc/intel/skylake: Enable UART debug controller on S3 resume | Furquan Shaikh | 2017-08-10 | 1 | -6/+20 |
| * | soc/intel/skylake: Use common/blocks/uart code | Aamir Bohra | 2017-05-09 | 1 | -28/+2 |
| * | soc/intel/skylake: Add CPU, PCH, MCH, IGD, XHCI and UART IDs for SKL/KBL HALO... | Sooi, Li Cheng | 2017-02-16 | 1 | -0/+3 |
| * | tree: drop last paragraph of GPL copyright header | Patrick Georgi | 2015-10-31 | 1 | -4/+0 |
| * | skylake: fix serial port with new code base | Aaron Durbin | 2015-08-13 | 1 | -4/+5 |
| * | skylake: Fix building without serial console | Duncan Laurie | 2015-07-24 | 1 | -1/+2 |
| * | Skylake: Only support UART2 as debug port, clean up the rest | Naveen Krishna Chatradhi | 2015-07-21 | 1 | -12/+1 |
| * | soc/intel: Add Skylake SOC support | Lee Leahy | 2015-07-16 | 1 | -0/+76 |
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index : coreboot.git | |
| Coreboot firmware sources | coreboot |
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