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path: root/src/soc/intel/skylake
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* soc/intel/skl; mb/google/eve,poppy: Update NHLT methodsMatt DeVillier2022-12-214-8/+25
* lib/nhlt, soc/intel/skl: Update NHLT to program feedback configMatt DeVillier2022-12-213-19/+52
* soc/intel/skylake/irq.c: Fix undefined `memcpy()`Angel Pons2022-12-171-8/+3
* soc/intel: Set IO APIC DMAR entry based on hwArthur Heymans2022-12-071-1/+1
* sb,soc/intel: Address TCO SECOND_TO_STS name collisionKyösti Mälkki2022-11-281-1/+1
* src/soc/intel: Remove unnecessary space after castsElyes Haouas2022-11-263-5/+5
* soc/intel: Add node_num to dimm_info struct + adjust dimm_info_fillDavid Milosevic2022-11-171-1/+2
* soc/intel: Include <cpu/cpu.h> instead of <arch/cpu.h>Elyes Haouas2022-11-042-5/+5
* soc/intel/skylake: Clean up includesElyes Haouas2022-11-0412-0/+16
* soc: Add SPDX license headers to MakefilesMartin Roth2022-10-313-0/+3
* payloads/edk2: Disable the CPU Timer Lib unless supportedSean Rhodes2022-10-221-0/+1
* treewide: Use 'fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk'Felix Held2022-10-151-1/+1
* treewide: Use 'fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk'Elyes Haouas2022-10-121-1/+1
* acpi/acpi_pm.c: refactor acpi_pm_state_for_* functionsFabio Aiuto2022-09-271-1/+1
* soc/intel/spi: Move BIOS flash SPI controllers to fast SPI driverWerner Zeh2022-09-221-2/+0
* soc/intel/skylake: Assign device ops in chipset devicetreeNico Huber2022-09-152-73/+70
* soc/intel/common/pch: Decouple CLIENT from BASEAngel Pons2022-07-201-1/+1
* soc/intel/skylake: Define macro TOTAL_PADSEric Lai2022-06-172-0/+4
* soc/intel: Rename heci_init to cse_initSubrata Banik2022-06-041-1/+1
* soc/intel/common/cpu: Use SoC overrides to set CPU privilege levelSubrata Banik2022-06-021-0/+16
* soc/intel/skylake: Move FSP_HYPERTHREADING to common Intel KconfigFelix Singer2022-05-261-4/+1
* soc/intel/skylake: Hook up FSP hyper-threading setting to option APIFelix Singer2022-05-171-1/+2
* soc/intel/*: Use SSDT to pass A4GB and A4GSArthur Heymans2022-05-163-4/+6
* soc/intel: Remove unused <cpu/intel/common/common.h>Elyes HAOUAS2022-05-161-1/+0
* soc/{amd/stoneyridge,intel}: Don't select VBOOT_SEPARATE_VERSTAGEArthur Heymans2022-04-291-1/+0
* soc/intel: Decouple HECI disabling interface from HECI disable KconfigSubrata Banik2022-04-291-1/+1
* soc/intel/{skl, xeon_sp}: Drop SoC specific LPC lock down configurationSubrata Banik2022-04-231-13/+0
* soc/intel: Remove unused <cbmem.h>Elyes HAOUAS2022-04-221-1/+0
* tpm: Refactor TPM Kconfig dimensionsJes B. Klinke2022-04-211-1/+1
* soc/intel: clean up dmi driver codeWonkyu Kim2022-04-201-1/+0
* Kconfig: Select UDK2017Patrick Rudolph2022-03-311-1/+1
* soc/intel: Move `pmc_clear_pmcon_sts()` into IA common codeSubrata Banik2022-03-292-18/+0
* src: Make PCI ID define names shorterFelix Singer2022-03-073-120/+120
* intelblocks/pcie: Correct mapping between LCAP port and coreboot indexMAULIK V VAGHELA2022-02-251-5/+5
* arch/x86: factor out and commonize HPET_BASE_ADDRESS definitionFelix Held2022-02-252-2/+1
* drivers/fsp/fsp2_0: Rework FSP Notify Phase API configsSubrata Banik2022-02-181-0/+3
* soc/intel/skylake: Add function to clear PMCON status bitsSubrata Banik2022-02-154-1/+20
* treewide: Remove "ERROR: "/"WARN: " prefixes from log messagesJulius Werner2022-02-071-2/+2
* cpu/x86/lapic: Move LAPIC configuration to MP initKyösti Mälkki2022-02-051-3/+0
* soc/intel/{adl, common}: Add routines into CSE IA-common codeSubrata Banik2022-02-041-0/+4
* soc/intel/skylake: Use PCR write to disable HECI1Subrata Banik2022-02-022-2/+4
* soc/intel/common/cse: Rework heci_disable functionSubrata Banik2022-02-021-0/+1
* soc/intel/skylake: move heci_init() from bootblock to romstageMatt DeVillier2022-01-272-4/+3
* soc/intel/common/cpu: Use SoC overrides to get CPU privilege levelSubrata Banik2022-01-192-0/+13
* soc/intel/skl: Replace dt `HeciEnabled` by `HECI1 disable` configSubrata Banik2022-01-163-13/+4
* src/soc/intel: Remove unused <console/console.h>Elyes HAOUAS2022-01-101-1/+0
* soc/intel/skylake/acpi: Replace Add(a,b) with ASL 2.0 syntaxFelix Singer2021-12-311-4/+2
* soc/intel/skylake/acpi: Use ASL 2.0 syntax to access arraysFelix Singer2021-12-301-2/+2
* soc/intel/{skl,cnl}: Guard USB macro parametersAngel Pons2021-12-261-1/+1
* soc/intel/{skylake/cannonlake}: Fix bug in vr_configAngel Pons2021-12-101-1/+1
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