| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | soc/intel/tigerlake: Correct IRQ interrupt | Wonkyu Kim | 2020-05-12 | 1 | -115/+121 |
| * | treewide: Remove "this file is part of" lines | Patrick Georgi | 2020-05-11 | 1 | -1/+0 |
| * | treewide: replace GPLv2 long form headers with SPDX header | Patrick Georgi | 2020-05-06 | 1 | -12/+1 |
| * | treewide: Move "is part of the coreboot project" line in its own comment | Patrick Georgi | 2020-05-06 | 1 | -2/+1 |
| * | soc/intel/tigerlake: Update interrupt setting | Wonkyu Kim | 2020-05-04 | 1 | -2/+2 |
| * | soc/intel/tigerlake/acpi: Fix typo in HDA in comment | Subrata Banik | 2020-04-07 | 1 | -2/+2 |
| * | soc/intel/tigerlake: Remove Jasper Lake SoC references | Aamir Bohra | 2020-04-01 | 1 | -5/+152 |
| * | soc: Remove copyright notices | Patrick Georgi | 2020-03-18 | 1 | -1/+0 |
| * | soc/tigerlake: Add IRQ header and ACPI support for JSP | Meera Ravindranath | 2020-02-19 | 1 | -152/+5 |
| * | soc/intel/tigerlake: Update interrupt info | Wonkyu Kim | 2020-01-22 | 1 | -74/+104 |
| * | soc/intel/tigerlake/acpi: Copy acpi directory from icelake | Subrata Banik | 2019-11-09 | 1 | -0/+138 |
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index : coreboot.git | |
| Coreboot firmware sources | coreboot |
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