coreboot.git - Coreboot firmware sources

	Commit message (Expand)	Author	Age	Files	Lines
*	soc/intel: Include <cpu/cpu.h> instead of <arch/cpu.h>	Elyes Haouas	2022-11-04	1	-2/+2
*	src: Make PCI ID define names shorter	Felix Singer	2022-03-07	1	-54/+54
*	soc/intel: Add TGL-H CPUID	Jeremy Soller	2021-08-24	1	-0/+1
*	soc/intel/common: Add TGL-H PCI IDs	Jeremy Soller	2021-08-19	1	-0/+13
*	soc/intel/tigerlake: Make use of `cpu/intel/cpu_ids.h'	Subrata Banik	2021-07-17	1	-1/+1
*	{nb,soc}/intel: Use get_current_microcode_rev() for ucode version	Subrata Banik	2020-08-05	1	-8/+2
*	soc/intel/tigerlake: Update Tiger Lake SA IDs	Derek Huang	2020-07-25	1	-3/+3
*	soc/intel/tigerlake: Add new IGD device	Ravi Sarawadi	2020-07-12	1	-0/+1
*	soc/intel/tigerlake: Remove unused EHL DID from TGL SoC	Subrata Banik	2020-07-04	1	-13/+0
*	soc/intel/tigerlake: Add CPU ID for TGL B0	Jamie Ryu	2020-06-06	1	-0/+1
*	treewide: Remove "this file is part of" lines	Patrick Georgi	2020-05-11	1	-1/+0
*	soc/intel/tigerlake: Use SPDX for GPL-2.0-only files	Angel Pons	2020-04-06	1	-13/+2
*	soc/intel/tigerlake: Remove Jasper Lake SoC references	Aamir Bohra	2020-04-01	1	-5/+0
*	soc: Remove copyright notices	Patrick Georgi	2020-03-18	1	-1/+0
*	soc/intel/common: Update Jasper Lake Device IDs	Meera Ravindranath	2020-02-25	1	-4/+5
*	soc/tigerlake: Add Device id for Tiger Lake Dual Core	Srinidhi N Kaushik	2020-02-17	1	-0/+1
*	soc/intel/common: Add Elkhartlake Device IDs	Tan, Lean Sheng	2020-01-22	1	-0/+13
*	soc/intel/common: Add Jasperlake Device IDs	rkanabar	2019-12-10	1	-0/+4
*	soc/intel/tigerlake: Include few more Tigerlake device IDs	Subrata Banik	2019-11-14	1	-3/+63
*	soc/intel/tigerlake/bootblock: Do initial SoC commit till bootblock	Subrata Banik	2019-11-09	1	-0/+168