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path: root/src/soc/intel/tigerlake/chip.h
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* treewide: Remove "this file is part of" linesPatrick Georgi2020-05-111-1/+0
* soc/intel/{jsl,tgl}: Rename PcdDebugInterfaceFlags macros for better understa...Subrata Banik2020-05-011-2/+2
* soc/intel/tigerlake: Fill PcieRpClkReqDetect from devicetreeMeera Ravindranath2020-05-011-0/+3
* soc/intel/tigerlake: Update iDisp Link UPD settingsSrinidhi N Kaushik2020-04-201-3/+0
* soc/intel/tigerlake: Remove eMMC/SD supportDuncan Laurie2020-04-171-9/+0
* soc/intel/tigerlake: Configure RP settingWonkyu Kim2020-04-141-0/+6
* soc/intel/tigerlake: Use SPDX for GPL-2.0-only filesAngel Pons2020-04-061-13/+2
* soc/intel/tigerlake: Configure IOM_TYPEC_SW_CONFIGURATION_3Brandon Breitenstein2020-03-301-0/+9
* soc/intel/tigerlake: Configure HyperthreadingWonkyu Kim2020-03-251-0/+2
* soc: Remove copyright noticesPatrick Georgi2020-03-181-1/+0
* soc/intel/tigerlake: Enable CNVi through dev_enabledSrinidhi N Kaushik2020-03-151-4/+0
* soc/intel/tigerlake: Update Cpu Ratio settingsSrinidhi N Kaushik2020-03-151-0/+12
* soc/intel/tigerlake: Configure L1Substates for PCH Root portsWonkyu Kim2020-03-121-0/+8
* soc/intel/tigerlake: Correct FSP log interfaceRonak Kanabar2020-03-111-0/+6
* soc/intel/tigerlake: Enable Hybrid storage modeWonkyu Kim2020-03-101-0/+5
* soc/intel/tigerlake: Enable CNVi ModeSrinidhi N Kaushik2020-03-061-0/+4
* src: capitalize 'PCIe'Elyes HAOUAS2020-03-041-1/+1
* soc/intel/tigerlake: Add Jasper lake GPIO supportRonak Kanabar2020-03-031-4/+4
* soc/intel/{icl,jsl,tgl}: Enable PlatformDebugConsent by KconfigSubrata Banik2020-03-011-11/+0
* soc/intel/tigerlake: Update FSP params for Jasper LakeMaulik V Vaghela2020-02-271-0/+9
* soc/intel/tigerlake: Enable Audio on TGLSrinidhi N Kaushik2020-02-171-13/+11
* soc/intel/tigerlake: Configure TCSS xHCI and xDCIWonkyu Kim2020-02-011-1/+5
* soc/intel/tigerlake: Enable DP ports according to board designWonkyu Kim2020-01-281-0/+26
* soc/intel/tigerlake: Update chip filesRavi Sarawadi2020-01-181-56/+25
* soc/intel/{cnl,icl,skl,tgl}: Remove unused gpe0_en_* from chip.hFurquan Shaikh2019-12-121-6/+0
* soc/intel/tigerlake: Do initial SoC commit till ramstageSubrata Banik2019-11-091-0/+280
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