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path: root/src/soc/intel/tigerlake/fsp_params.c
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* tigerlake: enable tcc_offset functionalitySumeet R Pawnikar2020-06-301-0/+3
* soc/soch/intel/tigerlake: Integrate PCIe hot-plug config UPDWonkyu Kim2020-06-171-0/+1
* soc/intel/tigerlake: Add devicetree support to change PCH VR settingsVenkata Krishna Nimmagadda2020-06-121-0/+23
* soc/intel/tigerlake: Set FSPS UPD ITbtConnectTopologyTimeoutInMsJohn Zhao2020-06-091-0/+7
* soc/intel/tigerlake: Configure THCWonkyu Kim2020-05-281-0/+18
* soc/intel/tigerlake: Disable VMDWonkyu Kim2020-05-261-0/+7
* soc/intel/tigerlake: Add FSP UPD D3HotEnable and D3ColdEnableJohn Zhao2020-05-261-0/+4
* tigerlake: enable DPTF functionality for volteerSumeet R Pawnikar2020-05-201-0/+3
* soc/tigerlake: Add devicetree configurability for IomTypeCPortPadCfgBrandon Breitenstein2020-05-201-1/+1
* soc/intel/tigerlake: Control SATA and DMI power optimizationShaunak Saha2020-05-121-0/+9
* treewide: Remove "this file is part of" linesPatrick Georgi2020-05-111-1/+0
* soc/intel/tigerlake: Fill PcieRpClkReqDetect from devicetreeMeera Ravindranath2020-05-011-0/+5
* soc/intel/tigerlake: Merge the recent change from other platformsWonkyu Kim2020-04-201-5/+13
* soc/intel/tigerlake: Implement CHIPSET_LOCKDOWNWonkyu Kim2020-04-141-0/+14
* soc/intel/tigerlake: Configure RP settingWonkyu Kim2020-04-141-2/+5
* soc/intel/tigerlake: Use SPDX for GPL-2.0-only filesAngel Pons2020-04-061-13/+2
* soc/intel/tigerlake: Remove Jasper Lake SoC referencesAamir Bohra2020-04-011-0/+213
* soc/intel/tigerlake: Select correct fsp_param as per SoC KconfigMaulik V Vaghela2020-01-131-46/+0
* soc/intel/tigerlake: Include soc common lpss header fileAamir Bohra2019-12-111-1/+1
* soc/intel/tigerlake: Do initial SoC commit till ramstageSubrata Banik2019-11-091-0/+46
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