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path: root/src/soc/intel/tigerlake/fsp_params.c
Commit message (Expand)AuthorAgeFilesLines
* soc/intel/tgl: Add PEG devices to PCI constraintsTim Crawford2022-05-281-0/+8
* soc/intel/tigerlake: add devicetree option PcieRpSlotImplementedMichael Niewöhner2022-01-141-0/+1
* soc/intel/tigerlake/fsp_params.c: Use `is_dev_enabled()`Felix Singer2022-01-011-4/+1
* soc/intel/tigerlake: Hook up DPTF device to devicetreeFelix Singer2021-12-091-1/+1
* intel/tigerlake: Add missing IRQ for CNViSean Rhodes2021-10-181-0/+1
* soc/intel: transition full control over PM Timer from FSP to corebootMichael Niewöhner2021-10-171-0/+9
* drivers/intel/fsp2_0: Refactor MultiPhaseSiInit API calling methodSubrata Banik2021-09-161-2/+2
* soc/intel/tigerlake: Move LPM functions to new fileTim Wawrzynczak2021-09-101-48/+2
* soc/intel/tigerlake: Lock PAM registers in finalizeTim Wawrzynczak2021-08-261-0/+1
* soc/intel/tigerlake: Add PCH-H GPIO definitionsJeremy Soller2021-08-241-1/+1
* soc/intel/tigerlake: Clean up FSP chipset lockdown configurationFelix Singer2021-08-121-11/+5
* soc/intel/tgl: Allow setting PCIe subsystem IDs after FSP-STim Crawford2021-08-121-0/+58
* soc/intel/*: Allow configuring 8254 timer via CMOSSean Rhodes2021-08-031-2/+5
* soc/intel/tigerlake: Make use of `cpu/intel/cpu_ids.h'Subrata Banik2021-07-171-1/+1
* soc/intel: Refactor `xdci_can_enable()` functionAngel Pons2021-07-011-4/+1
* soc/intel/tigerlake: Send End-of-Post message to CSETim Wawrzynczak2021-06-301-6/+6
* soc/intel/tigerlake: Enable support for common IRQ blockTim Wawrzynczak2021-06-291-1/+206
* soc/intel/tigerlake: Use devfn_disable() function for XDCISubrata Banik2021-06-231-8/+3
* soc/intel/tigerlake: Make use of is_devfn_enabled() functionSubrata Banik2021-06-161-17/+8
* soc/intel/tigerlake: Hook up FSP repositoryFelix Singer2021-06-101-1/+1
* soc/intel: Drop unused lpss functionsFurquan Shaikh2021-06-071-23/+0
* soc/intel/tigerlake: Allow devicetree to fill UPD related to TCSS OCNick Vaccaro2021-05-141-0/+6
* soc/intel/tgl,mb/google/volteer: Add API for Type-C aux bias padsTim Wawrzynczak2021-05-061-4/+8
* intel/tigerlake: Add Acoustic featuresShaunak Saha2021-04-061-6/+2
* soc/intel/tigerlake: Move TCSS code to intel/common/blockTim Wawrzynczak2021-03-281-3/+4
* soc/intel/tgl: Add configurable value for PmcUsb2PhySusPgEnableDerek Huang2021-03-191-0/+3
* soc/intel/tigerlake: Add CNVi Bluetooth flag at devicetree entryCliff Huang2021-03-151-8/+6
* soc/intel/tigerlake: Enable TCSS Muxes to disconnect mode during bootBrandon Breitenstein2021-03-051-1/+1
* soc/tigerlake: Fix TCSS code to calling back and forth to mainboard and socBrandon Breitenstein2021-03-051-3/+2
* soc/intel/tigerlake: Enable end of post support in FSPNick Vaccaro2021-02-221-0/+15
* soc/intel/tgl: Update S0ix enable mask based on SoC and mainboard designShreesh Chhabbi2021-02-101-1/+53
* soc/intel/tgl: Add configurable value for UsbTcPortEnBrandon Breitenstein2021-01-141-0/+1
* soc/intel/tigerlake: Disable TC cold supportSrinidhi N Kaushik2021-01-131-0/+3
* soc/intel/tigerlake: Enable USB2 port reset message on Type-C portsJohn Zhao2021-01-081-0/+3
* soc/intel/tigerlake: Expose UPD to enable Precision Time MeasurementDuncan Laurie2020-11-201-0/+1
* soc/intel/tigerlake: Add code for early tcssBrandon Breitenstein2020-11-131-0/+6
* soc/intel/tigerlake: Disable C1 C-state DemotionRavi Sarawadi2020-11-051-0/+4
* soc/intel/tigerlake: Add Acoustic featuresShaunak Saha2020-10-231-0/+8
* soc/intel/tigerlake: Add support for CnviBtCore and CnviBtAudioOffloadJohn Zhao2020-09-241-0/+7
* soc/intel/tigerlake: Configure FSP UPDs for minimum assertion widthsJamie Ryu2020-09-231-0/+17
* soc/intel: skl,cnl,icl,jsl,tgl: disable usb over-current pin by defaultMichael Niewöhner2020-09-061-2/+10
* soc/intel/tigerlake: Add mainboard hook for overriding SoC configJes Klinke2020-09-021-0/+6
* soc/intel/tigerlake: Allow fine grained control of S0iX statesJes Klinke2020-08-171-0/+8
* soc/intel/{icl,jsl,tgl}: Remove SkipMpInit UPD as deprecatedSubrata Banik2020-08-011-5/+1
* soc/intel/tigerlake: Configure TCSS D3Hot and D3ColdJohn Zhao2020-07-291-2/+8
* soc/intel/tigerlake: Simplify is-device-enabled checksFelix Singer2020-07-281-28/+8
* src: Update bare access to BOOL CONFIG_ vals to CONFIG()Martin Roth2020-07-261-3/+3
* soc/intel/tigerlake: Select PLATFORM_USES_FSP2_2Subrata Banik2020-07-211-0/+20
* soc/intel/tigerlake: Hook up SATA Port Enable DITO UPDsShaunak Saha2020-07-151-0/+24
* soc/intel/tigerlake: Disable hybrid storage mode in CSE Lite RO bootJamie Ryu2020-07-031-1/+15
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