coreboot.git - Coreboot firmware sources

	Commit message (Expand)	Author	Age	Files	Lines
*	soc/inte/*/gpio; Add GPE_EN and GPE_STS register definition	Maulik V Vaghela	2022-05-16	1	-0/+10
*	soc/intel/{xeon-sp,icl,tgl,jsl,ehl}: add NMI_{EN,STS} registers	Michael Niewöhner	2021-09-23	1	-0/+10
*	soc/intel/tigerlake: Add known CPU Port IDs for GPIO communities	Tim Wawrzynczak	2021-05-06	1	-0/+4
*	soc/intel/tigerlake: Add known GPIO virtual wire information	Tim Wawrzynczak	2021-05-06	1	-0/+27
*	treewide: Remove "this file is part of" lines	Patrick Georgi	2020-05-11	1	-1/+0
*	treewide: replace GPLv2 long form headers with SPDX header	Patrick Georgi	2020-05-06	1	-12/+1
*	treewide: Move "is part of the coreboot project" line in its own comment	Patrick Georgi	2020-05-06	1	-2/+1
*	soc/intel/tgl: Synchronize GPIO ASL table with Linux kernel	Shaunak Saha	2020-05-06	1	-13/+22
*	soc/intel/tigerlake: Remove Jasper Lake SoC references	Aamir Bohra	2020-04-01	1	-0/+197
*	soc/intel/tigerlake: Add Jasper lake GPIO support	Ronak Kanabar	2020-03-03	1	-198/+0
*	soc/intel/tigerlake: Fix GPIO communities	Shaunak Saha	2020-01-25	1	-58/+44
*	soc/intel/tigerlake: Update GPIO config	Ravi Sarawadi	2020-01-22	1	-6/+6
*	soc/intel/tigerlake: Do initial SoC commit till ramstage	Subrata Banik	2019-11-09	1	-0/+212