| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | soc/intel/tigerlake: Enable support for common IRQ block | Tim Wawrzynczak | 2021-06-29 | 1 | -4/+0 |
| * | soc/intel/tigerlake: Add IRQs for LPSS uart | Patrick Rudolph | 2020-08-12 | 1 | -0/+4 |
| * | soc/intel/tigerlake: Correct IRQ interrupt | Wonkyu Kim | 2020-05-12 | 1 | -60/+0 |
| * | treewide: Remove "this file is part of" lines | Patrick Georgi | 2020-05-11 | 1 | -1/+0 |
| * | soc/intel/tigerlake: Update interrupt setting | Wonkyu Kim | 2020-05-04 | 1 | -7/+8 |
| * | soc/intel/tigerlake: Use SPDX for GPL-2.0-only files | Angel Pons | 2020-04-06 | 1 | -13/+2 |
| * | soc/intel/tigerlake: Remove Jasper Lake SoC references | Aamir Bohra | 2020-04-01 | 1 | -5/+64 |
| * | soc: Remove copyright notices | Patrick Georgi | 2020-03-18 | 1 | -1/+0 |
| * | soc/tigerlake: Add IRQ header and ACPI support for JSP | Meera Ravindranath | 2020-02-19 | 1 | -64/+5 |
| * | soc/intel/tigerlake: Update interrupt info | Wonkyu Kim | 2020-01-22 | 1 | -76/+54 |
| * | soc/intel/tigerlake: Do initial SoC commit till ramstage | Subrata Banik | 2019-11-09 | 1 | -0/+106 |
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index : coreboot.git | |
| Coreboot firmware sources | coreboot |
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