| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | soc/intel/tgl: Select CSE defined ME spec version for tigerlake | Dinesh Gehlot | 2023-02-24 | 1 | -83/+0 |
| * | soc/intel/tgl: Move ME FSR structures to pertinent header | Dinesh Gehlot | 2023-02-04 | 1 | -84/+0 |
| * | soc/intel/tigerlake: Clean up includes | Elyes Haouas | 2022-10-25 | 1 | -2/+2 |
| * | soc/intel/{adl,ehl,tgl}: Rename spi_protection_mode to mfg_mode | Subrata Banik | 2022-01-02 | 1 | -2/+2 |
| * | treewide: Remove "this file is part of" lines | Patrick Georgi | 2020-05-11 | 1 | -1/+0 |
| * | soc/intel: Replace GPLv2 long form headers with SPDX header | Elyes HAOUAS | 2020-05-08 | 1 | -12/+1 |
| * | treewide: Move "is part of the coreboot project" line in its own comment | Patrick Georgi | 2020-05-06 | 1 | -2/+1 |
| * | soc/intel/tigerlake: Add function to dump ME firmware status information | Krishna Prasad Bhat | 2020-04-14 | 1 | -0/+161 |
| * | soc/intel/{icl,tgl}: Make use of print_me_fw_version() from CSE lib | Krishna Prasad Bhat | 2020-04-14 | 1 | -0/+19 |
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index : coreboot.git | |
| Coreboot firmware sources | coreboot |
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