coreboot.git - Coreboot firmware sources

	Commit message (Expand)	Author	Age	Files	Lines
*	soc/intel: Rename heci_init to cse_init	Subrata Banik	2022-06-04	1	-1/+1
*	soc/intel: Drop `romstage_pch_init()` function	Angel Pons	2021-03-01	1	-2/+3
*	soc/intel/tigerlake: Enable CSE Lite driver for TGL platform in romstage	Sridhar Siricilla	2020-12-14	1	-1/+12
*	soc/intel: remove duplicate weak versions of mainboard_get_dram_part_num()	Nick Vaccaro	2020-10-05	1	-6/+0
*	mb, soc: change mainboard_get_dram_part_num() prototype	Nick Vaccaro	2020-10-05	1	-5/+8
*	soc/intel/tigerlake: Rename pch_init() code	Alexey Buyanov	2020-08-26	1	-1/+1
*	treewide: Remove "this file is part of" lines	Patrick Georgi	2020-05-11	1	-1/+0
*	soc/intel/tigerlake: Allow mainboard to override DRAM part number	Marco Chen	2020-04-07	1	-2/+23
*	soc/intel/tigerlake: Use SPDX for GPL-2.0-only files	Angel Pons	2020-04-06	1	-13/+2
*	soc: Remove copyright notices	Patrick Georgi	2020-03-18	1	-1/+0
*	soc/intel/tigerlake: Save DIMM info by available nodes	Jamie Ryu	2020-03-11	1	-33/+40
*	soc/intel/tigerlake/romstage: Do initial SoC commit till romstage	Subrata Banik	2019-11-09	1	-0/+128