coreboot.git - Coreboot firmware sources

	Commit message (Expand)	Author	Age	Files	Lines
*	soc/intel: Replace `SA_PCIEX_LENGTH` Kconfig options	Angel Pons	2021-01-30	1	-1/+1
*	soc/intel/tigerlake: Set power limits for Tiger Lake Y-SKU	Sumeet R Pawnikar	2020-07-25	1	-0/+6
*	soc/intel/tigerlake: Update Tiger Lake SA IDs	Derek Huang	2020-07-25	1	-4/+3
*	mb/google/volteer: Override power limits with SKU-specific limits	Tim Wawrzynczak	2020-06-22	1	-1/+27
*	soc/intel/common: Improve Type16 SMBIOS tables	Patrick Rudolph	2020-05-28	1	-0/+14
*	soc/intel/tigerlake: Move PMC PCI resources under PMC device	Tim Wawrzynczak	2020-05-20	1	-11/+0
*	tigerlake: update processor power limits configuration	Sumeet R Pawnikar	2020-05-20	1	-0/+12
*	treewide: Remove "this file is part of" lines	Patrick Georgi	2020-05-11	1	-1/+0
*	soc/intel/tigerlake: Use SPDX for GPL-2.0-only files	Angel Pons	2020-04-06	1	-13/+2
*	soc: Remove copyright notices	Patrick Georgi	2020-03-18	1	-1/+0
*	soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI table	John Zhao	2020-03-12	1	-1/+9
*	soc/intel/tigerlake: Do initial SoC commit till ramstage	Subrata Banik	2019-11-09	1	-0/+73