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path: root/src/soc/intel/tigerlake
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* soc/intel/tigerlake: Use devfn_disable() function for XDCISubrata Banik2021-06-231-8/+3
* soc/intel/{alderlake,tigerlake}: Fix typo in pmc.hWerner Zeh2021-06-171-1/+1
* soc/intel/tigerlake: Make use of is_devfn_enabled() functionSubrata Banik2021-06-163-53/+22
* util: Add DDR4 generic SPD for MT40A512M16TB-062E:RWisley Chen2021-06-141-0/+2
* soc/intel/tigerlake: Move MAX_CPUS to KconfigAndy Pont2021-06-101-0/+4
* soc/intel/tigerlake: Hook up FSP repositoryFelix Singer2021-06-103-37/+52
* cpu/x86: Default to PARALLEL_MP selectedKyösti Mälkki2021-06-071-1/+0
* soc/intel: Drop unused lpss functionsFurquan Shaikh2021-06-071-23/+0
* soc/intel/tigerlake: Return TBT PowerResource from PR0 and PR3John Zhao2021-05-272-14/+20
* soc/intel/tigerlake: Add validity for TBT firmware authenticationJohn Zhao2021-05-261-0/+4
* cpu/x86: Only include smm code if CONFIG_HAVE_SMI_HANDLER=yArthur Heymans2021-05-181-1/+0
* soc/intel/tigerlake: Allow devicetree to fill UPD related to TCSS OCNick Vaccaro2021-05-143-0/+23
* src: Match array format in function declarations and definitionsPatrick Georgi2021-05-131-1/+1
* soc/intel/{adl,tgl,jsl}: Enable power button smi after BS_CHIPS_EXITKane Chen2021-05-072-2/+13
* soc/intel/{adl,tgl,jsl}: Add smihandler_soc_disable_busmasterKane Chen2021-05-071-0/+8
* soc/intel/tgl,mb/google/volteer: Add API for Type-C aux bias padsTim Wawrzynczak2021-05-064-15/+29
* soc/intel/tigkerlake: Add IOM PCR PIDTim Wawrzynczak2021-05-061-0/+1
* soc/intel/tigerlake: Add known CPU Port IDs for GPIO communitiesTim Wawrzynczak2021-05-062-0/+10
* soc/intel/tigerlake: Add known GPIO virtual wire informationTim Wawrzynczak2021-05-061-0/+27
* soc/intel/*: Update data types for variables holding PCH_DEVFN_* macrosTim Wawrzynczak2021-05-031-1/+1
* device: Switch pci_dev_is_wake_source to take pci_devfn_tTim Wawrzynczak2021-05-031-21/+8
* soc/intel/tigerlake: Use device ID from pci_devs header fileJohn Zhao2021-04-261-4/+5
* soc/intel: Replace open-coded buffer length calculationAngel Pons2021-04-211-4/+2
* soc/intel: Fix typo in commentAngel Pons2021-04-211-1/+1
* soc/intel/alderlake: rename CONFIG_MAX_PCIE_CLOCKS to CONFIG_MAX_PCIE_CLOCK_SRCRizwan Qureshi2021-04-213-4/+4
* soc/intel/tigerlake: Fix devices list in the DMAR DRHD structureJohn Zhao2021-04-211-14/+14
* dptf: Move platform-specific information to `struct dptf_platform_info`Tim Wawrzynczak2021-04-132-0/+19
* intel/tigerlake: Add Acoustic featuresShaunak Saha2021-04-062-15/+10
* soc/intel/tigerlake: Fix REG_BASE_SIZETim Wawrzynczak2021-03-281-1/+1
* soc/intel/tigerlake: Move TCSS code to intel/common/blockTim Wawrzynczak2021-03-285-499/+4
* soc/intel: Rename and move MISCCFG_GPIO_PM_CONFIG_BITS definition to soc/gpio.hSubrata Banik2021-03-272-1/+7
* soc/intel/tigerlake: Add #include guards to soc/early_tcss.hTim Wawrzynczak2021-03-221-0/+5
* util: Add DDR4 generic SPD for H4AAG165WB-BCWENick Vaccaro2021-03-221-0/+1
* soc/intel/tgl: Add configurable value for PmcUsb2PhySusPgEnableDerek Huang2021-03-192-0/+5
* soc/intel/tigerlake: Remove obsolete CNVi Bluetooth PCI deviceCliff Huang2021-03-153-4/+0
* soc/intel/tigerlake: Add CNVi Bluetooth flag at devicetree entryCliff Huang2021-03-152-8/+9
* soc/intel/*: drop UART pad configuration from common codeMichael Niewöhner2021-03-121-34/+6
* soc/intel/tigerlake: Enable TCSS Muxes to disconnect mode during bootBrandon Breitenstein2021-03-055-53/+118
* soc/tigerlake: Fix TCSS code to calling back and forth to mainboard and socBrandon Breitenstein2021-03-053-14/+26
* soc/intel/tigerlake: Fix NULL being passed for response bufferFurquan Shaikh2021-03-051-18/+14
* soc/intel: Factor out common smmrelocate.cAngel Pons2021-03-033-251/+1
* soc/intel/tigerlake: Re-use existing define in CrashLog implementationFrancois Toguo2021-03-031-2/+2
* soc/intel: Retype `CnviBtAudioOffload` devicetree optionAngel Pons2021-03-031-4/+1
* soc/intel: Drop `bootblock_cpu_init()` functionAngel Pons2021-03-014-27/+2
* soc/intel: Drop `romstage_pch_init()` functionAngel Pons2021-03-014-14/+3
* soc/intel: Factor out common smbus.hAngel Pons2021-03-011-30/+3
* soc/intel: Factor out common gpe.hAngel Pons2021-03-011-114/+1
* soc/intel: Factor out identical acpigen GPIO helpersAngel Pons2021-03-012-37/+1
* soc/intel: Include gfx.asl from northbridgeAngel Pons2021-03-011-3/+0
* soc/intel/*/smmrelocate.c: Sync includesAngel Pons2021-02-241-9/+9
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