| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | soc/intel/xeon_sp/acpi: Refactor Xeon-SP ASL file location | Shuo Liu | 2024-05-06 | 1 | -33/+0 |
| * | soc/intel/xeon_sp/acpi: Break out the ACPI PCH IRQ ASL | Marc Jones | 2020-10-06 | 1 | -0/+1 |
| * | soc/intel/xeon_sp/acpi: Rename pci_irq.asl | Marc Jones | 2020-10-03 | 1 | -1/+1 |
| * | soc/intel/xeon_sp: Use common ASL code for xeon_sp | Marc Jones | 2020-10-03 | 1 | -0/+32 |
| * | soc/intel/xeon_sp: Refactor code to allow for additional CPUs types | Andrey Petrov | 2020-03-26 | 1 | -46/+0 |
| * | soc: Remove copyright notices | Patrick Georgi | 2020-03-18 | 1 | -2/+0 |
| * | soc/intel: Add Intel Xeon Scalable Processor support | Jonathan Zhang | 2020-03-06 | 1 | -0/+48 |
 |
index : coreboot.git | |
| Coreboot firmware sources | coreboot |
| summaryrefslogtreecommitdiffstats |