| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | soc/xeon_sp/skx: Define MSR PPIN related registers | Johnny Lin | 2020-06-02 | 1 | -0/+9 |
| * | treewide: Remove "this file is part of" lines | Patrick Georgi | 2020-05-11 | 7 | -7/+0 |
| * | soc/intel/xeon_sp: make CPX ramstage.h common for CPX, SKX | Michael Niewöhner | 2020-05-11 | 1 | -17/+0 |
| * | treewide: replace GPLv2 long form headers with SPDX header | Patrick Georgi | 2020-05-06 | 6 | -72/+6 |
| * | treewide: Move "is part of the coreboot project" line in its own comment | Patrick Georgi | 2020-05-06 | 6 | -12/+6 |
| * | acpi: Move ACPI table support out of arch/x86 (3/5) | Furquan Shaikh | 2020-05-02 | 2 | -2/+2 |
| * | xeon_sp, ocp/tiogapass: remove unused FSP-style GPIO defs | Maxim Polyakov | 2020-05-01 | 1 | -298/+0 |
| * | device: Constify struct device * parameter to write_acpi_tables | Furquan Shaikh | 2020-04-28 | 1 | -1/+1 |
| * | soc/intel/xeon_sp: Use SPDX for GPL-2.0-only files | Angel Pons | 2020-04-06 | 1 | -14/+2 |
| * | soc/intel/xeon_sp: Refactor code to allow for additional CPUs types | Andrey Petrov | 2020-03-26 | 9 | -0/+783 |
 |
index : coreboot.git | |
| Coreboot firmware sources | coreboot |
| summaryrefslogtreecommitdiffstats |