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* soc/intel/skylake: Make use of `cpu/intel/cpu_ids.h'Subrata Banik2021-07-172-2/+1
* soc/intel/tigerlake: Make use of `cpu/intel/cpu_ids.h'Subrata Banik2021-07-173-3/+3
* soc/intel/alderlake: Make use of `cpu/intel/cpu_ids.h'Subrata Banik2021-07-173-3/+1
* cpu/intel: Add dedicated file to grow Intel CPUIDsSubrata Banik2021-07-174-54/+5
* soc/intel/xeon_sp/cpx: Align Cooper Lake CPUID as per EDSSubrata Banik2021-07-171-2/+2
* soc/intel/alderlake: Add virtual GPIOs for community 1Maulik V Vaghela2021-07-152-223/+281
* soc/intel/tigerlake: Use `is_devfn_enabled()` for Crashlog UPDsSubrata Banik2021-07-151-4/+2
* soc/intel/alderlake: Use `is_devfn_enabled()` for Crashlog UPDsSubrata Banik2021-07-151-4/+2
* src: use mca_clear_status function instead of open codingFelix Held2021-07-141-4/+1
* soc/intel/alderlake: Add GFx Device ID 0x46a6Maulik V Vaghela2021-07-142-0/+2
* soc/intel/common: Use SPR for backing up data way and eviction maskSubrata Banik2021-07-141-6/+6
* soc/intel/skylake: Drop dead `ScanExtGfxForLegacyOpRom`Angel Pons2021-07-141-1/+0
* soc/intel/skylake: Rename `Rmt` devicetree settingAngel Pons2021-07-142-2/+2
* soc/intel/common/block/cpu/cpulib: use mca_get_bank_count()Felix Held2021-07-141-3/+1
* include/cpu/x86/msr: introduce IA32_MC_*(x) macrosFelix Held2021-07-141-2/+2
* src: Use initial_lapicid() instead of open coding itArthur Heymans2021-07-141-3/+2
* soc/intel/alderlake: Implement WA for DDR5 DIMM modulesMeera Ravindranath2021-07-131-0/+27
* soc/intel/alderlake: Add (and fix) devices in IRQ tableTim Wawrzynczak2021-07-131-6/+51
* soc/intel/alderlake: Increase PRERAM_CBMEM_CONSOLE_SIZE to 8KBSubrata Banik2021-07-121-1/+1
* soc/intel/common/irq: Program IRQ pin in irq_program_non_pch()Tim Wawrzynczak2021-07-121-4/+6
* soc/intel/alderlake: Add missing devices to pci_devs.hTim Wawrzynczak2021-07-121-0/+26
* soc/intel/alderlake: Set max Pkg C-states to AutoV Sowmya2021-07-122-0/+19
* soc/intel/alderlake: Avoid NULL pointer deferenceJohn Zhao2021-07-081-4/+4
* arch/x86: Use ENV_X86_64 instead of _x86_64_Patrick Rudolph2021-07-061-1/+1
* soc/intel/alderlake: Add support to update the FIVR configsV Sowmya2021-07-052-0/+89
* soc/intel/alderlake: Correct Bus and Device of Touch Host ControllerVarshit B Pandya2021-07-052-6/+6
* arch/x86: Add X86_CUSTOM_BOOTMEDIARaul E Rangel2021-07-022-17/+7
* src: Introduce `ARCH_ALL_STAGES_X86`Angel Pons2021-07-0213-13/+0
* soc/intel/common/block/cse: Add ME EOP timestampsTim Wawrzynczak2021-07-021-0/+3
* soc/intel/alderlake: Add USB TCSS enablementBernardo Perez Priego2021-07-021-0/+14
* soc/intel/alderlake: Enable energy efficiency turbo modeV Sowmya2021-07-011-0/+2
* soc/intel: Refactor `xdci_can_enable()` functionAngel Pons2021-07-0110-35/+16
* soc/intel/alderlake: Select VBOOT_X86_SHA256_ACCELERATION configSubrata Banik2021-07-011-0/+1
* soc/intel/jasperlake: Send End-of-Post message to CSETim Wawrzynczak2021-06-302-5/+6
* soc/intel/tigerlake: Send End-of-Post message to CSETim Wawrzynczak2021-06-302-6/+7
* soc/intel/alderlake: Send End-of-Post message to CSETim Wawrzynczak2021-06-302-1/+16
* soc/intel/common/block/cse: Add BWG error recovery to EOP failureTim Wawrzynczak2021-06-303-0/+92
* soc/intel/elkhartlake: Enable PCH GBELean Sheng Tan2021-06-305-3/+68
* soc/intel/common: Refine pmc_get_xtal_freq functionLean Sheng Tan2021-06-302-5/+20
* soc/intel/common: Move PMC EPOC related code to Intel common codeLean Sheng Tan2021-06-3011-64/+41
* src: Move `select ARCH_X86` to platformsAngel Pons2021-06-3013-0/+13
* soc/intel/tigerlake: Enable support for common IRQ blockTim Wawrzynczak2021-06-297-168/+224
* soc/intel/alderlake: Enable support for common IRQ blockTim Wawrzynczak2021-06-297-212/+206
* soc/intel/cannonlake: Use new IRQ moduleTim Wawrzynczak2021-06-298-254/+233
* soc/intel/cannonlake: Add some missing DEVFN macrosTim Wawrzynczak2021-06-291-0/+12
* soc/intel/common/irq: Add function to return IRQ for PCI devfnTim Wawrzynczak2021-06-292-1/+19
* soc/intel/common/irq: Internally cache PCI IRQ resultsTim Wawrzynczak2021-06-292-23/+52
* soc/intel/common/irq: Add function to program north PCI IRQsTim Wawrzynczak2021-06-292-0/+21
* soc/intel/common/block/irq: Add support for intel_write_pci0_PRTTim Wawrzynczak2021-06-293-0/+54
* soc/intel/common: Add new IRQ moduleTim Wawrzynczak2021-06-294-0/+402
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